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作 者:夏经华 查祎英 桑玲 杨霏 吴军民 Xia Jinghua;Zha Yiying;Sang Ling;Yang Fei;Wu Junmin(State Key Laboratory of Advanced Power Transmission Technology,Beijing 102209,China;Global Energy Interconnection Research Institute Co.,Ltd.,Beijing 102209,China)
机构地区:[1]先进输电技术国家重点实验室,北京102209 [2]全球能源互联网研究院有限公司,北京102209
出 处:《微纳电子技术》2020年第8期604-608,共5页Micronanoelectronic Technology
基 金:国家电网有限公司总部科技资助项目(5455GB170004)。
摘 要:使用p+n-n+外延结构制备了10 kV4H-SiC pin二极管,在室温下通过时间分辨光致发光(TRPL)谱法在低掺杂外延层中测量载流子寿命,根据晶圆上大量二极管的电容-电压测量值估算掺杂浓度,采用深能级瞬态谱(DLTS)法获得了影响载流子寿命的主要缺陷的俘获截面、浓度和复合中心能级位置。通过将TRPL测量得到的载流子寿命用于二极管电流-电压特性的计算机辅助工艺设计(TCAD)模拟中,并与根据DLTS测得的深能级缺陷参数估算的Shockley-Read-Hall(SRH)载流子寿命进行比较发现,载流子寿命除了受位于0.67 eV(EC-ET)能级的碳空位缺陷控制外,更受到其他深能级缺陷的影响。10 kV4 H-SiC pin diodes were fabricated using p+n-n+epitaxial structures.The carrier lifetime was measured in the low doped epitaxial layer by the time resolved photoluminescence(TRPL)method at room temperature.The doping concentration was estimated by capacitance-voltage measurements on a large number of diodes across the wafer.In addition,the deep level transient spectroscopy(DLTS)method was used to obtain the capture cross section,concentration and recombination center level position of the main defect affecting carrier lifetime.Carrier lifetimes obtained by TRPL measurements were used in technology computer aided design(TCAD)simulations of the diode current-voltage characteristics and compared with the ShockleyRead-Hall(SRH)carrier lifetimes estimated by the measured deep-level defect parameters with the DLTS.Besides the carbon vacancy defect at 0.67 eV(EC-ET),it is found that the carrier lifetime is also affected by other deep-level defects.
关 键 词:4H-SIC PIN二极管 载流子寿命 碳空位 深能级缺陷
分 类 号:TN31[电子电信—物理电子学] TN304.24
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