一种新型栅压自举采样开关  

A Novel Bootstrapped Sampling Switch

作　　者：周前能[1] 高唱 李红娟[1] 唐政维[1] ZHOU Qianneng;GAO Chang;LI Hongjuan;TANG Zhengwei(Department of Microelec.,Chongqing Univ.of Posts and Telecommunications,Chongqing400065,P.R.China)

机构地区：[1]重庆邮电大学微电子系,重庆400065

出　　处：《微电子学》2020年第4期482-485,共4页Microelectronics

基　　金：重庆市重点产业共性关键技术创新专项项目(cstc2017zdcy-zdyf0166);重庆市技术创新与应用示范项目(cstc2018jszx-cyztzx0049)。

摘　　要：基于SMIC 0.18μm CMOS工艺,设计了一种新型的栅压自举采样开关。采用镜像结构,增加了自举电容。采用时钟控制反相器,减少了MOS采样开关管的栅极节点寄生电容。这些措施有效抑制了电荷共享效应,提高了线性度,提高了采样开关的导通、关断速度。仿真结果表明,在6.25 MHz频率、0.8 V输入正弦波信号、100 MHz采样频率的条件下,该栅压自举采样开关的SFDR为111.3 dBc,SNDR为108.9 dB。A novel bootstrapped sampling switch was designed in SMIC 0.18 μm CMOS process. A "mirror" architecture was used to increase the bootstrap capacitance. Clocked-inverters were used to reduce the parasitic capacitance at the gate node of MOS sampling switch transistor. By adopting these techniques, the charge-sharing effect was effectively suppressed, the linearity was improved, and the on speed or off speed of the bootstrapped sampling switch were increased. Simulation results showed that the designed bootstrapped sampling switch achieved a spurious free dynamic range(SFDR) of 111.3 dBc and a signal-to-noise-distortion ratio(SNDR) of 108.9 dB when the input sinusoidal signal had a frequency of 6.25 MHz and a peak-peak voltage of 0.8 V, and the sampling frequency was 100 MHz.

关 键 词：电荷共享 无杂散动态范围 信噪失真比 栅压自举采样开关 

分 类 号：TN432[电子电信—微电子学与固体电子学]