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作 者:王玲 成建兵[1] 陈明[1] 张才荣 邓志豪 WANG Ling;CHENG Jianbing;CHEN Ming;ZHANG Cairong;DENG Zhihao(College of Electronic and Optical Engineering&College of Microelectronics,Nanjing University of Posts and Telecommunications,Nanjing 210023,P.R.China)
机构地区:[1]南京邮电大学电子与光学工程学院微电子学院,南京210023
出 处:《微电子学》2020年第5期720-725,共6页Microelectronics
基 金:国家自然科学基金资助项目(61274080)。
摘 要:为满足高速、高集成度和低EMI的要求,提出了一种分离栅VDMOS器件。通过在JFET区集成梳状MOS电容、漂移区电阻,构成内部集成RC吸收器,减小了器件关断过程中漏端电压斜率dVds/dt和电流斜率dId/dt。仿真结果表明,相比于常规VDMOS,该VDMOS的漏端过冲电压从535 V降低到283 V,抖动频率从42 MHz降低到33 MHz,抖动持续时间从65 ns缩短到30 ns。A novel spilt-gate VDMOS structure was proposed to meet the requirements of high speed,high integration and low EMI.The voltage slope dVds/dt and current slope dId/dt had been reduced during device turn-off by integrating an internal RC snubber consisting of a comb-shaped MOS capacitor and a drift region resistor in the JFET region.The simulation results showed that compared with the conventional VDMOS,the drain overshoot of the proposed VDMOS was decreased from 535 V to 283 V,the oscillation frequency was reduced from 42 MHz to 33 MHz,and the oscillation duration was shortened from 65 ns to 30 ns.
分 类 号:TN386[电子电信—物理电子学]
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