Design of GGNMOS ESD protection device for radiationhardened 0.18 μm CMOS process  

作　　者：Jianwei Wu Zongguang Yu Genshen Hong Rubin Xie 

机构地区：[1]The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi 214035,China

出　　处：《Journal of Semiconductors》2020年第12期57-64,共8页半导体学报（英文版）

基　　金：This work was supported by the Military Quality Engineering of China(No.1807WR0002).

摘　　要：In this paper,the ESD discharge capability of GGNMOS(gate grounded NMOS)device in the radiation-hardened 0.18μm bulk silicon CMOS process(Rad-Hard by Process:RHBP)is optimized by layout and ion implantation design.The effects of gate length,DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation.The size of DCGS,multi finger number and single finger width of ESD verification structures are designed,and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology.Finally,the optimized GGNMOS is verified on the DSP circuit,and its ESD performance is over 3500 V in HBM mode.

关 键 词：total ionizing dose RHBP GGNMOS ESD ion implantation STI TLP leakage current DCGS 

分 类 号：TN386[电子电信—物理电子学]