提高多芯片拼接线性度的新方法  

A New Method of Enhancing Linearity for Multi Chip Integration Stitching and Splicing

作　　者：高慧莹[1] 左宁[1] 艾博[1] GAO Huiying;ZUO Ning;AI Bo(The 45^(th)Research Institute of CETC,Beijing 100176,China)

机构地区：[1]中国电子科技集团公司第四十五研究所,北京100176

出　　处：《电子工业专用设备》2021年第1期15-19,共5页Equipment for Electronic Products Manufacturing

摘　　要：为实现多芯片集成高精度拼接,对芯片拼接线性度进行了深入研究,提出了一种保证高精度芯片集成拼接方法。通过CCD图像匹配、识别定位每个芯片的实际位置坐标,根据已经拼接完成的芯片位置坐标拟合,进行芯片逐步预定位,及时纠偏,拼接完成后进行每一行芯片的直线度和行与行之间平行度的检测,介绍了芯片集成拼接工艺流程和拼接方法,并对检测算法进行了仿真分析,实例验证,证明该拼接方法的可行性。In order to realize multi chips integration high precision stitching,the actual position coordinates of each chip is recognized,positioned and matched image by CCD,according to the chip position coordinates that have been stitched,the chips are pre-positioned step by step,correcting timely,linearity of each row and parallelism of between rows are inspected after stitching completion.After Stitching and Splicing,with simulation analysis and case verification show this method is feasible.

关 键 词：芯片拼接 预定位 直线度 平行度 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]