基于FPGA的ASIC芯片抗辐射性能评估系统  

ASIC Chip Anti-Irradiation Performance Evaluation System Based on FPGA

作　　者：刘海静[1] 王正 单毅[1] 董业民[1] Liu Haijing;Wang Zheng;Shan Yi;Dong Yemin(Shanghai Institute of Microsystem and Information Technology,Chinese Academy of Sciences,Shanghai 200050,China)

机构地区：[1]中国科学院上海微系统与信息技术研究所,上海200050

出　　处：《半导体技术》2021年第3期249-254,共6页Semiconductor Technology

摘　　要：针对航天电子控制系统对集成电路的抗辐射需求,设计了一种基于现场可编程门阵列(FPGA)的全新架构的专用集成电路(ASIC)抗辐射性能评估系统。该系统基于FPGA高性能、高速度、高灵活性和大容量的特性,不仅具备传统芯片评估系统的能力,还具备精确判定失效事件发生时刻、被测ASIC时序、内部状态及大致的内部路径位置的能力。对该系统进行单粒子翻转(SEU)辐射试验,试验结果表明,在81.4 MeV·cm^(2)·mg^(-1)的线性能量转移阈值下,该系统能自动判别没有发生SEU事件。目前,该系统已成功应用于自研高可靠性ASIC芯片抗辐射性能的评估。Aiming at the anti-irradiation requirements of the aerospace electronic control system for integrated circuits,an anti-irradiation performance evaluation system with a novel architecture for application specific integrated circuit(ASIC)based on field programmable gate array(FPGA)was designed by taking advantage of the characteristics of the existing FPGA,such as high performance,high speed,high flexibility and large capacity.While having the capabilities of the conventional chip evaluation systems,the new system is also capable of determining the time of failure event accurately,the tested ASIC timing,internal state and approximate location of internal path.Single event upset(SEU)performance of the system was evaluated through the critical linear energy transfer threshold.The test results validate that under the LET threshold of 81.4 MeV·cm^(2)·mg^(-1),the system can automatically determine that no SEU event has occurred on the ASIC chip.The developed system has been successfully applied to the anti-irradiation performance evaluation of high reliable ASIC chip.

关 键 词：专用集成电路(ASIC) 抗辐射 现场可编程门阵列(FPGA) 单粒子翻转(SEU) 性能评估 

分 类 号：TM92[电气工程—电力电子与电力传动] TM07