基于FPGA的水平集图像分割算法加速器  

A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation

作　　者：刘野 肖剑彪 吴飞[1] 常亮[1] 周军[1] LIU Ye;XIAO Jianbiao;WU Fei;CHANG Liang;ZHOU Jun(University of Electronic Science and Technology of China,Chengdu 611731,China)

机构地区：[1]电子科技大学,成都611731

出　　处：《电子与信息学报》2021年第6期1525-1532,共8页Journal of Electronics & Information Technology

基　　金：国家自然科学基金委员会-中国工程物理研究院NSAF联合基金(U2030204)。

摘　　要：水平集算法因其出色的性能,在图像分割领域中得到了广泛的应用。同时,与基于深度学习的图像分割算法相比,水平集算法不需要训练数据,大幅降低了数据标记带来的工作量。然而,目前水平集算法主要是基于软件开发,涉及大量复杂的计算,以及计算的多次迭代,导致较高的处理延时与功耗。为了加快水平集算法的处理速度和降低功耗,该文提出了一种基于FPGA的水平集图像分割算法加速器,其中包含4个设计创新点:任务级并行处理、图像分块像素级并行处理、全流水线处理架构、分时复用的梯度和散度算子处理。实验结果表明,与在CPU上执行的水平集算法相比,该文提出的硬件加速器处理速度提升10.7倍,功耗仅为2.2 W。The level set algorithm is widely used for image segmentation due to its high accuracy.In addition,compared to the deep learning-based image segmentation methods,the level set algorithm can be implemented without training data,which reduces significantly the labeling efforts.However,the normal level set algorithm is still developed using software,involving complex computation with a large number of pixels and iterations andcausing long processing time and large power consumption.In this work,an FPGA-based level set hardware accelerator is proposed for image segmentation.The proposed hardware accelerator contains four design components:task-level parallel processing,image splitting processing,fully-pipelined processing architecture,and time-multiplexed gradient and divergence processing engine.Based on the experimental results,the proposed hardware accelerator achieves up to 10.7 times acceleration compared to the level set algorithm executing on the CPU,with only 2.2 W power consumption.

关 键 词：FPGA 硬件加速器 水平集 图像分割 

分 类 号：TN47[电子电信—微电子学与固体电子学]