结构对钙钛矿压电薄膜电学性能影响的研究进展  

Influence of Structure on the Electrical Properties of Perovskite Piezoelectric Films:a Review

作　　者：米庆博 邢志国 王海斗 金国[1] 郭伟玲 黄艳斐 唐诗 MI Qingbo;XING Zhiguo;WANG Haidou;JIN Guo;GUO Weiling;HUANG Yanfei;TANG Shi(Institute of Surface/Interface Science andTechnology,College of Material Science and Chemical Engineering,Harbin Engineering University,Harbin150006,China;National Key Laboratory for Remanufacturing,Armored Forces Engineering Institute,Beijing 100072,China;CNPC Research Institute of Safety&Environment Technology Co.,Ltd,Beijing 102206,China)

机构地区：[1]哈尔滨工程大学,表面技术与腐蚀工程研究所,材料科学与化学工程学院,哈尔滨150006 [2]中国人民解放军陆军装甲兵学院,装备再制造技术国防科技重点实验室,北京100072 [3]中国石油集团安全环保技术研究院,北京102206

出　　处：《材料导报》2021年第15期15065-15071,共7页Materials Reports

基　　金：国家自然科学基金面上项目(51775554);国家自然科学基金重点项目(51535011);中央高校基金(HEUCF)。

摘　　要：钙钛矿结构的压电陶瓷具有压电系数高、机电耦合性能良好、性能稳定可靠等优点,其应用环境广泛,是当前重要的商用传感器及半导体元件制造材料之一。其中薄膜结构的钙钛矿压电材料的尺寸小,有利于集成复杂电路结构,在精密电子元件的制造上具有不可替代的优势。然而,宏观上的尺寸降低、界面间的晶格失配以及成型过程中产生的气孔缺陷限制了畴壁的运动,致使薄膜材料表现出较低的铁电、压电、介电特性。近年来,研究者不断调整基体的种类并探索压电薄膜成型工艺的改进方法,试图优化压电薄膜因受结构特点限制而降低的电学性能。研究认为,(100)、(110)、(111)是能够有效促进薄膜电学特性提升的晶粒取向,同时柱状的晶粒形状和大的晶粒尺寸能够进一步保证薄膜获得良好的电学性能。晶粒形状和晶粒尺寸强烈依赖于薄膜的厚度,而薄膜厚度的增加有利于各项电学性能的提升。另外,晶粒尺寸与薄膜厚度类似,二者均存在一临界值,在该值以下,电学响应几乎消失。界面处的失配应变导致的失配位错限制了电畴的运动,低介电常数层降低了薄膜的静电存储能力,是导致薄膜的电特性下降的重要因素。薄膜中孔隙的钉扎效应提高了新畴形核长大的能量势垒,同时也将抑制压电薄膜中四方相向菱形相的转变,这使得孔隙在降低压电薄膜压电系数(d_(33))的同时,也有可能增强薄膜的热稳定性。此外,近年来的研究发现,薄膜的机械耦合性能与孔隙率存在正相关关系。文中针对压电陶瓷薄膜结构及结构特征产生的应力对其性能的影响进行论述,阐述了薄膜晶体结构、几何结构及缺陷分别对材料电学性能的影响,分析了薄膜内部微区结构对畴壁运动的作用机制。随着智能制造行业的快速发展,压电陶瓷薄膜势必向着尺寸更小、结构设计更复杂、使用范围更�Perovskite piezoelectric ceramic has become one of the important materials for commercial sensors and semiconductor devices due to their high piezoelectric coefficient and good electromechanical coupling performance.Perovskite piezoelectric film is small in size,which is beneficial to the integration of complex circuit structure and has irreplaceable advantages in the manufacture of precision electronic components.However,the decrease of macro size,the lattice mismatch between the interfaces and pore defects in the formation process limit the movement of domain walls,resulting in the low ferroelectric,piezoelectric and dielectric properties of the films.In recent years,researchers have been constantly adjusting the selection of substrates,exploring ways to improve the formation process of piezoelectric thin film,in order to optimize the electrical properties of piezoelectric thin film limited by structural characteristics.The results show that(100),(110)and(111)are the grain orientations which can effectively improve the electrical properties of the films.At the same time,the columnar grain shape and large grain size can further ensure the piezoelectric films obtain good electrical properties.The shape and size of the grains depend on the thickness of the film to a great extent,so the increase of thin film thickness is beneficial to improving the electrical properties.In addition,the grain size is similar to the film thickness,both of which have a critical value.Below this value,the electrical response nearly disappears.The mismatch dislocation caused by the mismatch strain at the interface limits the movement of the domain,and the low dielectric constant layer reduces the electrostatic storage capacity of the film,which is an important factor leading to the decline of the electrical properties of the film.The pinning effect of holes increases the energy barrier for nucleation and growth of new domains,and inhibits the transition of piezoelectric thin films from tetragonal phase to rhombic phase.Therefore,althoug

关 键 词：压电薄膜 晶粒取向 尺寸 晶格失配 缺陷 

分 类 号：TB34[一般工业技术—材料科学与工程]