基于混合压缩结构的新型浮点乘法器设计  

Design of a new floating point multiplier based on hybrid compression structure

作　　者：姚上上 沈立 YAO Shangshang;SHEN Li(Department of Electronic Science and technology,University of Defense Science andtechnology,Changsha 410073,China)

机构地区：[1]国防科技大学电子科学与技术系,湖南长沙410073

出　　处：《微电子学与计算机》2021年第9期74-78,共5页Microelectronics & Computer

摘　　要：为了进一步提高浮点乘法器的性能,缩短浮点乘法器关键路径延时,提出了一种基于新型4-2压缩器和5-2压缩器的混合压缩结构.在Xillinx的xc7a35tcsg324开发板上,基于该结构实现了IEEE754标准的32位浮点乘法器.相较于现有的压缩方式,提出的新型压缩结构相较于现有的压缩方式,所使用的LUT资源减少了45,关键路径延时减少了0.004 ns.与传统浮点乘法器相比,关键路径延时由6.022 ns缩短至4.673 ns,提升了浮点乘法器的运算性能.In order to further improve the performance of Floating-Point Multiplier and shorten the critical path delay of Floating-Point Multiplier, a hybrid compression structure based on new 4-2 compressor and 5-2 compressor is proposed. On the xc7 a35 tcsg324 development board of xillinx, the 32-bit Floating-Point Multiplier of IEEE754 standard is implemented based on this structure. Compared with the existing compression methods, the LUT resource and critical path delay are reduced by 45 and 0.004 ns respectively. Compared with the traditional Floating-Point Multiplier, the critical path delay is reduced from 6.022 ns to 4.673 ns, which improves the performance of the Floating-Point Multiplier.

关 键 词：4-2压缩器 5-2压缩器 WALLACE树 浮点乘法器 

分 类 号：TN492[电子电信—微电子学与固体电子学]