基于异构FPGA的目标检测硬件加速器架构设计  

Architecture Design of Target Detection Hardware Accelerator Based on Heterogeneous FPGA

作　　者：夏琪迪 颜秉勇[1] 周家乐 王慧锋[1] XIA Qidi;YAN Bingyong;ZHOU Jiale;WANG Huifeng(School of Information Science and Engineering,East China University of Science and Technology,Shanghai 200237,China)

机构地区：[1]华东理工大学信息科学与工程学院,上海200237

出　　处：《华东理工大学学报（自然科学版）》2021年第6期706-715,共10页Journal of East China University of Science and Technology

基　　金：国家重点研发计划(2018YFC1803306);青年科学基金(61906068)。

摘　　要：采用粗细粒度优化、参数定点化与重排序等多种硬件加速方法,基于FPGA+SOC异构平台提出了一种低功耗目标检测加速器架构。针对现有研究的设计局限性,在Zynq 7000系列FPGA上对YOLOv2算法进行新型多维度硬件加速,并对加速器性能和资源耗费进行深入分析建模,验证架构的合理性;为充分利用片上硬件资源,对各个模块进行特定优化设计,针对被忽视的底层繁琐数据访问,改进加速器数据访存机制,有效减少了系统传输时延。实验结果表明,该架构在PYNQ-Z2平台上获得了26.98 GOPs的性能,比现有的基于FPGA的目标检测平台提高了约38.71%,功耗仅为2.96 W,对目标检测算法的实际应用具有深远意义。In recent years,with the continuous breakthrough in the field of algorithms,the current target detection algorithms have higher and higher computational complexity.In the forward inference stage,many practical applications often face low latency and strict power consumption restrictions.How to realize a low-power,low-cost,and high-performance target detection platform has gradually attracted more attention.As a high-performance,reconfigurable and low-cost embedded platform,Field Programmable Gate Array(FPGA)is becoming the key technology of algorithm application.In view of the above requirements,this paper proposes a low-power target detection accelerator architecture based on FPGA+SOC(System On Chip)heterogeneous platform by adopting various hardware acceleration methods such as coarse and fine granularity optimization,parameter fixed-point and reordering.Aiming at the design limitation of existing researches on Zynq 7000 series FPGA,this paper proposes a new multi-dimensional hardware acceleration of YOLOv2(You Only Look Once)algorithm,and deeply analyzes and models the accelerator performance and resource consumption to verify the rationality of the architecture.In order to make full use of the on-chip hardware resources to optimize the design of each module,the accelerator data access mechanism is improved to effectively reduce the transmission delay of the system and improve the actual utilization rate of bus bandwidth.The fixed-point processing of floating-point numbers can reduce the processing load of FPGA and further accelerate the processing speed.It is shown via experiments that the architecture achieves 26.98 GOPs performance on PYNQ-Z2 platform,which is about 38.71%higher than the existing FPGA-based target detection platform,and the power consumption is only 2.96 W.Moreover,it has far-reaching significance for the application of target detection algorithm.

关 键 词：现场可编辑门阵列 目标检测 硬件加速 高层次综合 

分 类 号：TP183[自动化与计算机技术—控制理论与控制工程] TP368.2[自动化与计算机技术—控制科学与工程]