64位双精度矩阵分解的优化和硬件实现  

Optimization and hardware implementation of 64-bit double-precision matrix decomposition

作　　者：邱俊豪 宋宇鲲[1,2] 陈文杰 侯宁 QIU Junhao;SONG Yukun;CHEN Wenjie;HOU Ning(Institute of VLSI Design, Hefei University of Technology, Hefei 230601, China;IC Design Web-cooperation Research Center of Ministry of Education, Hefei University of Technology, Hefei 230601, China;School of Electrical and Control Engineering, Henan University of Urban Construction, Pingdingshan 467000, China)

机构地区：[1]合肥工业大学微电子设计研究所,安徽合肥230601 [2]合肥工业大学教育部IC设计网上合作研究中心,安徽合肥230601 [3]河南城建学院电气与控制工程学院,河南平顶山467000

出　　处：《合肥工业大学学报（自然科学版）》2021年第12期1640-1645,共6页Journal of Hefei University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(61874156)。

摘　　要：矩阵分解是线性代数中最重要的运算之一,广泛应用于现代通讯和控制。文章提出一种针对浮点矩阵的GR-QR(Givens rotation QR)分解一维线性结构,利用GR-QR分解运算过程中的并行特点,提高运算资源利用率,实现任意阶浮点矩阵分解,并设计实现了基于此结构的矩阵分解电路,该电路支持2-32阶双精度浮点矩阵的直接分解。在TSMC28 nm工艺,QR分解器的工作主频为700 MHz,面积为2 mm^(2),计算精度达到10^(-15),性能是1.6 GHz RTX2070的95倍。Matrix decomposition is one of the most important operations in linear algebra,and is widely used in modern communications and control.This paper presents a one-dimensional linear structure of Givens rotation QR(GR-QR)decomposition for floating-point matrices.It uses the parallel characteristics of GR-QR decomposition in the operation process to improve the utilization of computing resources and achieve arbitrary-order floating-point matrix decomposition.And a matrix decomposition circuit based on this structure is designed and implemented,which supports direct decomposition of 2-32 order double-precision floating-point matrix.In the TSMC28 nm process,the working frequency of the QR resolver is 700 MHz,the area is 2 mm^(2),the calculation accuracy reaches 10^(-15),and its performance is 95 times that of the 1.6 GHz RTX2070.

关 键 词：QR分解 Givens旋转 ASIC实现 硬件加速 一维线性结构 

分 类 号：TN47[电子电信—微电子学与固体电子学]