LPWAN芯片中Keeloq硬件加速器的实现  

Implementation of Keeloq Hardware Accelerator in LPWAN Chip

作　　者：李建军 王锐 李志华 LI Jianjun;WANG Rui;LI Zhihua(Unicmicro(Guangzhou)Co.,Ltd.,Guangdong 510555,China)

机构地区：[1]广芯微电子(广州)股份有限公司,广东510555

出　　处：《集成电路应用》2021年第12期1-3,共3页Application of IC

摘　　要：阐述LPWAN技术背景,重点分析了Keeloq加、解密算法,探讨在LPWAN芯片中设计更好的Keeloq硬件加速器,从而达到提升效率降低功耗,满足低功耗物联网应用的需求。This paper expounds the technical background of LPWAN, focuses on the analysis of Keeloq encryption and decryption algorithms, and discusses the design of better Keeloq hardware accelerator in LPWAN chip, so as to improve efficiency, reduce power consumption and meet the needs of low-power Internet of things applications.

关 键 词：集成电路设计 LPWAN KEELOQ 低功耗 硬件加速器 

分 类 号：TN402[电子电信—微电子学与固体电子学] P391.44[天文地球—地球物理学]