基于SiP技术的多片DDR3高速动态存储器设计  

Design of Multi-Chip DDR3 High-Speed Dynamic Memory Based on SiP Technology

作　　者：张小蝶 邱颖霞 许聪[1,2] 邢正伟 ZHANG Xiaodie;QIU Yingxia;XU Cong;XING Zhengwei(Anhui Siliepoch Technology Co.,Ltd.,Hefei 230000,China;The 38th Institute of CETC,Hefei 230088,China)

机构地区：[1]安徽芯纪元科技有限公司,合肥230000 [2]中国电子科技集团公司第三十八研究所,合肥230088

出　　处：《电子与封装》2022年第1期39-44,共6页Electronics & Packaging

摘　　要：基于系统级封装(System in Package,SiP)技术,结合自研自主可控DSP处理器“魂芯”II-A和多片DDR3颗粒,详细介绍了一款高速动态存储控制一体化SiP设备的设计方案和仿真验证分析结果。重点介绍了此款SiP的电路拓扑设计、版图设计,并从拓扑结构波形仿真、DDR3时序裕量计算、与板级实现方案对比三方面对其PCB后仿进行了分析和验证,仿真结果符合规范要求,证明了所采用的Fly-By拓扑适用于CPU与多片DDR3颗粒所组成的一体化SiP设备,且SiP设备性能优于板级实现方案。Based on the system in package(SiP)technology,combined with a self-developed independent controllable DSP processor("HX"II-A)and multi-chip DDR3 particles,the design scheme and simulation verification analysis of a high-speed dynamic memory control integrated SiP is introduced in detail.Focused on the circuit topology design and the layout design of this SiP,its PCB post-simulation is verified from three aspects,including topology simulation waveform,DDR3 timing margin calculation,and comparison with board-level implementation schemes.The simulation results are compounded and standardized,and the requirements prove that the adopted Fly-By topology is suitable for integrated SiP equipment which is composed of CPU and multiple DDR3 particles.In addition,the performance of SiP equipment is better than the board-level implementation scheme.

关 键 词：DDR3 高速电路 SIP 信号完整性 Sigrity仿真 

分 类 号：TN454[电子电信—微电子学与固体电子学]