一种用于直接射频采样ADC的多模式数字下变频器设计  

A Design of Multi-Mode Digital Down Converter for Direct RF-Sampling ADC

作　　者：彭庆尧 吴旦昱[1,2] 周磊 武锦[1,2] 刘新宇 PENG Qingyao;WU Danyu;ZHOU Lei;WU Jin;LIU Xinyu(Institute of Microelectronics,Chinese Academy of Science,Beijing 100029,China;School of Microelectronics,University of Chinese Academy of Science,Beijing 100049,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学微电子学院,北京100049

出　　处：《电子器件》2021年第6期1314-1321,共8页Chinese Journal of Electron Devices

摘　　要：为满足直接射频采样ADC对数字下变频器(digital down converter, DDC)抽取模式数量的需求,提出了一种多模式DDC设计。首先研究和分析了AD采样原理、DDC原理和高速高精度数控振荡器原理,建立了基于多模式抽取滤波器组的DDC模型,并进行了行为级仿真和分析;之后采用Verilog HDL完成了RTL设计与仿真,利用Synopsys数字后端工具链完成了基于28 nm工艺的版图设计与后仿。仿真显示,该设计可工作在1 GHz时钟下,实现了14种模式,最低阻带衰减大于100 dB,在抽取系数为2的条件下,-3 dB带宽达到478.867 MHz。包含ADC所需的其他数字电路的总面积为1 300μm×1 370μm(DDC约占67%),总仿真功耗为301.7 mW。该设计具有抽取模式多、功耗低、消耗资源少的优点,能够满足直接射频采样ADC对多模式DDC的需求。In order to meet the demand of direct RF-sampling ADC for the number of decimation modes of DDC,a multi-mode DDC design is proposed. The principles of AD sampling, DDC and high-speed and high-precision NCO are studied and analyzed, the DDC model based on multi-mode decimation filter bank is established, and the behavior level simulation and analysis are carried out, then the RTL design and simulation using Verilog HDL are completed, and the layout design and post simulation based on 28 nm using the digital back-end tool chain of Synopsys are completed. Simulation result shows that the design can work at 1 GHz with 14 modes. The minimum stopband attenuation is more than 100 dB,and the-3 dB bandwidth reaches 478.867 MHz when the decimation is 2. The area of DDC is 67% of 1 300 μm×1 370 μm. The power consumption under simulation is 301.7 mW. The design can meet the demand of direct RF-sampling ADC for multi-mode DDC,and has the advantages of more modes, less power consumption, and less resource consumption.

关 键 词：数字下变频器 有限冲激响应数字滤波器 坐标旋转数字计算方法 28 nm工艺 

分 类 号：TN911[电子电信—通信与信息系统] TN492[电子电信—信息与通信工程]