界面电荷对圆柱形高k VDMOS的影响仿真研究  

Simulation Study on the Effect of Interface Charge on Cylindrical High k VDMOS

作　　者：刘乙 LIU Yi(Lab.of Integr.Circ.Design,Department of Electrical Engineering,Southwest Jiaotong Univ.,Chengdu 610000,P.R.China)

机构地区：[1]西南交通大学电子工程系集成电路设计实验室,成都610000

出　　处：《微电子学》2022年第1期109-114,共6页Microelectronics

基　　金：国家自然科学基金资助项目(60906009)。

摘　　要：相比于传统VDMOS,超结耐压层结构和高k介质耐压层结构VDMOS能实现更高的击穿电压和更低的导通电阻。通过仿真软件,对3D圆柱形高k VDMOS具有、不具有界面电荷下的各种结构参数对电场分布、击穿电压和比导通电阻的影响进行了系统总结。研究和定性分析了击穿电压和比导通电阻随参数的变化趋势及其原因。对比导通电阻和击穿电压的折中关系进行了优化。该项研究对高k VDMOS的设计具有参考价值。Compared with traditional VDMOS, the superjunction and high k dielectric structure VDMOS could achieve higher breakdown voltage and lower on-resistance. The effects of various structural parameters on electric field distribution, breakdown voltage and specific on-resistance of 3 D cylindrical high k VDMOS with and without interfacial charges were systematically summarized by simulation software. The variation trend and reason of breakdown voltage and specific on-resistance with parameters were studied and qualitatively analyzed. This study provided a reference for the design of high k VDMOS.

关 键 词：高介电常数耐压层 界面电荷 击穿电压 比导通电阻 

分 类 号：TN386[电子电信—物理电子学]