应用于高精度模数转换器的乘法数模单元模块研究  

Research on Multiplying Digital-to-Analog Converter for High Precision Analog-To-Digital Converter

作　　者：邵杰 唐路 SHAO Jie;TANG Lu(School of Microelectronics,Southeast University,Nanjing 210096,China;School of Information Engineering,Southeast University,Nanjing 210096,China)

机构地区：[1]东南大学微电子学院,南京210096 [2]东南大学信息科学与工程学院,南京210096

出　　处：《电子与封装》2022年第4期53-58,共6页Electronics & Packaging

基　　金：国家重点研发课题“微弱电信号精密检测及高速数据处理技术(2018YFB2003300)”子课题“超高速和高精度模数转换器设计技术研究(2018YFB2003302)”。

摘　　要：提出了一种应用于18 bit 20 MS/s无采保结构(SHA-Less)高精度流水线型(Pipeline)模数转换器(Analog-to-Digital Converter,ADC)的乘法数模单元(Multiplying Digital-to-Analog Converter,MDAC)。从减小电路动态、静态误差以及系统噪声的角度,介绍了高性能MDAC电路的设计方法。使用0.18μm CMOS工艺实现电路版图,并用Spectre和Calibre进行后仿验证。在室温条件下,输入5 MHz正弦波信号,采样频率为20 MHz,对设计的MDAC电路进行后端仿真并进行快速傅里叶变换(Fast Fourier Transform,FFT)处理,结果显示信噪比(Signal Noise Ratio,SNR)为87.32 d B,有效位数(Effective Number of Bits,ENOB)为13.97 bit,无杂散动态范围(Spurious Free Dynamic Range,SFDR)为90.53 d Bc,总谐波失真(Total Harmonic Distortion,THD)为-90.74 d B。A multiplying digital-to-analog converter(MDAC)for 18 bit 20 MS/s SHA-less high precision pipeline analog-to-digital converter(ADC)is proposed.In order to reduce dynamic errors,static errors and system noise,the design method of high performance switching capacitor circuit is introduced.The circuit layout is realized using 0.18μm CMOS process and verified by Spectre and Calibre.At room temperature,the MDAC circuit is simulated and processed by FFT at the back end with input of 5 MHz sine wave signal and sampling frequency of 20 MHz.The results show that the signal noise ratio(SNR)is 87.32 d B,the effective number of bits(ENOB)is 13.97 bit,the spurious free dynamic range(SFDR)is 90.53 d Bc and the total harmonic distortion(THD)is-90.74 d B.

关 键 词：高精度 流水线型模数转换器 乘法数模单元 

分 类 号：TN432[电子电信—微电子学与固体电子学]