一种进位链TDC的实现及其抽头方式研究  

Research of a carry chain TDC and its tap method

作　　者：李海涛[1] 李斌康[1,2] 田耕 阮林波[1,2] 吕宗璟 Li Haitao;Li Binkang;Tian Geng;Ruan Linbo;Lv Zongjing(Northwest Institute of Nuclear Technology,Xi′an 710024,China;State Key Laboratory of Intense Pulsed Radiation Simulation and Effect,Xi′an 710024,China)

机构地区：[1]西北核技术研究所,陕西西安710024 [2]强脉冲辐射环境模拟与效应国家重点实验室,陕西西安710024

出　　处：《电子技术应用》2022年第4期53-56,61,共5页Application of Electronic Technique

摘　　要：采用Xilinx公司的Kintex-7内部的进位链,实现了时间数字转换器(Time to Digital Converter,TDC)。采用码密度校准方法 对TDC进行逐位校准,标定了TDC的码宽。码密度校准过程中发现,不同的进位链抽头位置会导致TDC的码宽不同、非线性不同,研究了2抽头、 4抽头方式下的TDC的码宽和非线性,在“0tap+3tap”的2抽头方式下,TDC可以获得较好的线性,时间分辨率为25 ps(对应最低有效位(Least Significant Bit,LSB)),微分非线性范围为-0.84~3.1 LSB,积分非线性范围为-5.2~2.2 LSB。A time to digital converter(TDC)is implemented using carry chains in Xilinx Kinex-7 FPGA.FPGA-TDC is calibrated bin-by-bin through the code density calibration method.In the calibration process,it is found that different carry chain tap modes will lead to different code widths and nonlinearity of TDC.The code widths and nonlinearity of TDC in 2-tap and 4-tap modes are studied.In the"0tap+3tap"2-tap mode,the FPGA-TDC can obtain the optimal nonlinearity with a time resolution of 25 ps(corresponding to least significant bit(LSB)),differential nonlinearity(DNL)ranges-0.84~3.1 LSB,integral nonlinearity(INL)ranges-5.2~2.2 LSB.

关 键 词：进位链 时间数字转换器 码密度校准 抽头方式 温度计码 冒泡现象 非线性 

分 类 号：TN79[电子电信—电路与系统]