28nm体硅工艺组合逻辑电路单粒子瞬态脉冲宽度研究  

Investigation of Single Event Transient Pulse Widthon 28nm Bulk CMOS Combinational Logic Circuits

作　　者：李同德 赵元富 王亮[1,2] 舒磊 苑靖爽[1,2] 黄昊 王维 LI Tongde;ZHAO Yuanfu;WANG Liang;SHU Lei;YUAN Jingshuang;HUANG Hao;WANG Wei(Beijing Institute of Microelectronics Technology,Beijing 100076,China;China Academy of Aerospace Electronics Technology,Beijing 100094,China;Laboratory of Science and Technology on Radiation Hardened Integrated Circuits,CASC,Beijing 100094,China)

机构地区：[1]北京微电子技术研究所,北京100076 [2]中国航天电子技术研究院,北京100094 [3]中国航天科技集团有限公司抗辐射集成电路技术试验室,北京100094

出　　处：《现代应用物理》2022年第1期105-109,共5页Modern Applied Physics

基　　金：国家自然科学基金资助项目(11690045,61674015,11690040)。

摘　　要：随着工艺的进步,由单粒子瞬态(single event transient,SET)导致的软错误占比越来越高,因此,针对SET的加固十分重要。组合逻辑电路中由辐射导致的脉冲宽度分布特征成为纳米集成电路抗辐射加固设计的主要参考参数之一。设计了一款28 nm体硅工艺单粒子瞬态脉冲宽度检测电路,包括数字电路中常用的反相器、与非门和或非门3种类型的组合逻辑单元,并考虑了驱动能力和输入个数,电路还包括宽量程和高精度的脉冲宽度检测结构。经单粒子效应试验,获得了单粒子辐射在不同逻辑单元中产生的脉冲宽度。试验结果表明:测试电路中的最大脉冲宽度为234 ps,器件组合形式及版图风格等因素导致脉冲宽度不同。分析了器件叉指结构和P管串联结构等组合形式或版图风格对脉冲宽度的影响。A detection circuit of the single event transient(SET)pulse width is designed based on 28 nm bulk silicon CMOS process,including three types of combinational logic units commonly used in digital circuits:inverter,NAND gate,and NOR gate.The driving ability and the number of inputs are considered.The circuit also includes a pulse width detection structure with wide range and high precision.Through the single event effect experiment,the pulse width of single event radiation in different logic units is obtained.The test results show that the maximum pulse width in the test circuit is 234 ps,and the pulse width is different due to the combination form of devices and layout style.The influence mechanism of device combination form and layout style on pulse width is analyzed.The research results provide a reference for the radiation hardened design of integrated circuits based on 28 nm bulk silicon process.

关 键 词：28nm体硅 组合逻辑电路 辐射试验 单粒子瞬态 脉冲宽度 

分 类 号：TN43[电子电信—微电子学与固体电子学] TL99[核科学技术—核技术及应用]