面向光通信应用的CMOS 28 Gbps低功耗高抖动容限CDR电路设计  

A CMOS 28 Gbps Low Power and High Jitter Tolerance CDR Circuit in Optical Communication Applications

作　　者：朱智宇 郭凯乐 武宇轩 刘涛[2] 吴苗苗 陆德超 ZHU Zhiyu;GUO Kaile;WU Yuxuan;LIU Tao;WU Miaomiao;LU Dechao(Information and Navigation School,Air Force Engineering University,Xi’an 710077,China;Air Defense and Antimissile School,Air Force Engineering University,Xi’an 710051,China)

机构地区：[1]空军工程大学信息与导航学院,西安710077 [2]空军工程大学防空反导学院,西安710051

出　　处：《空军工程大学学报（自然科学版）》2022年第2期77-82,共6页Journal of Air Force Engineering University(Natural Science Edition)

基　　金：国家重点研发计划(2018YFB2202302)。

摘　　要：为了解决光模块中高功耗芯片恶化激光调制器性能,以及解决收发端时钟基准偏差导致误码率高的问题,设计了一款低功耗高抖动容限的时钟数据恢复电路(CDR)。通过采用压控振荡器(VCO)型全速时钟的CDR系统架构和电感峰化的时钟缓冲技术,降低了CDR芯片的功耗;通过在CDR积分通路中引入零点补偿电阻,提高了CDR的抖动容限。该CDR采用CMOS 65nm工艺设计和1.1V电源供电,后端仿真结果表明:当CDR电路工作在28Gbps时,功耗是2.18pJ/bit,能容忍的固定频差是5 000ppm,恢复时钟的抖动峰峰值是5.6ps,抖动容限达到了设计指标,且满足CIE-25/28G协议规范。Aimed at the problems that the performance of laser modulator with high-power chips in optical modules becomes deteriorated,and bit-error-rate caused by the clock reference deviation between transceivers is high,a low power and high jitter tolerance clock and data recovery circuit(CDR)is proposed in this paper.By adopting a technology of voltage-controlled oscillator(VCO)type and full-speed CDR system architecture,and using a technology of an inductance peaking in clock buffer,the power consumption of the CDR chip is reduced.By introducing a zero point compensation resistor in the CDR integration path,the jitter tolerance of the CDR is improved.The CDR is designed with CMOS 65nm process and supplied with 1.1V.The back-end simulation results show that when the CDR circuit works at 28Gbps,the power consumption is 2.18pJ/bit.When the frequency difference of the transceiver is 5 000ppm,the jitter peak-to-peak value of the recovered clock is 5.6ps,and the jitter tolerance meets the needs of design index and the CIE-25/28Gprotocol specification.

关 键 词：高速串行接口 时钟数据恢复电路 压控振荡器 窄带缓冲器 

分 类 号：TU458[建筑科学—岩土工程]