一种流水线型ADC的时序改进技术研究  

Study on a Timing Optimization Technique for Pipelined ADC

作　　者：岂飞涛 刘涛[1,2] 朱蓓丽[1,2] 张琳 刘海南 滕瑞[1,2] 李博[1,2] 赵发展 罗家俊[1,2] 韩郑生[1,2,3] QI Feitao;LIU Tao;ZHU Beili;ZHANG Lin;LIU Hainan;TENG Rui;LI Bo;ZHAO Fazhan;LUO Jiajun;HAN Zhengsheng(Institute of Microelec.,Chinese Academy of Sci.,Beijing 100029,P.R.China;Key Lab.of Sci.and Technol.on Silicon Devices,Chinese Academy of Sci.,Beijing 100029,P.R.China;Univ.of Chinese Academy of Sci.,Beijing 100049,P.R.China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院硅器件技术重点实验室,北京100029 [3]中国科学院大学,北京100049

出　　处：《微电子学》2022年第2期217-222,共6页Microelectronics

摘　　要：对一种流水线型模数转换器(ADC)的时序电路进行了改进研究。改进时序延长了余量增益单元MDAC部分加减保持相位的时长,可以在不增加功耗与面积的情况下,将一种10位流水线型ADC在20 MS/s采样率下的有效位(ENOB)从9.3位提高到9.8位,量化精度提高了5%;将该ADC有效位不低于9.3位的最高采样率从21 MS/s提高到29 MS/s,转换速度提高了35%。ADC的采样频率越高,改进时序带来的效果越显著。该项技术特别适用于高速高精度流水线型ADC,也为其他结构ADC的高速高精度设计提供思路。A timing optimization technique was studied based on 10 bit pipelined ADC. The technique prolonged the phase holding time of MDAC. Without increasing power consumption and chip area, the effective numbers of bit(ENOB) was increased from 9.3 bit to 9.8 bit under 20 MS/s sampling rate of a 10 bit pipelined ADC, and the accuracy was improved by 5%. The maximum sampling rate of the ADC was increased from 21 MS/s to 29 MS/s with ENOB no less than 9.3 bit, and the speed was increased by 35%. The higher the sampling rate of ADC, the more significant the improvement effect was. This technique was especially suitable for high-speed and high-precision pipelined ADC, and also provided ideas for high-speed and high-precision design optimization of ADC.

关 键 词：流水线型模数转换器 改进型时序 高速高精度 

分 类 号：TN792[电子电信—电路与系统]