基于缓冲器拓扑的低偏斜时钟树算法研究  

Study on Low Skew Clock Tree Algorithm Based on Buffer Topology

作　　者：董辰 DONG Chen(Shanghai Anlu Information Technology Co.,Ltd.,Shanghai 200434,China)

机构地区：[1]上海安路信息科技股份有限公司,上海200434

出　　处：《集成电路应用》2022年第8期24-27,共4页Application of IC

摘　　要：阐述一种基于迷宫布线算法的时钟树生成算法,该算法集成了缓冲器插入、缓冲器驱动能力和拓扑生成,并能够考虑一般缓冲器插入位置,以实现稳健的时钟偏斜控制。探讨用于预估延迟和斜率的准确时序分析引擎以及用于在时钟树综合期间更好地减少偏移的平衡布线方案,可以通过缓冲器驱动能力进行积极的缓冲器插入,并保持准确的延迟信息和低偏移。实验结果表明,综合结果不仅满足信号完整性约束,而且保持合理的偏斜。This paper presents a clock tree generation algorithm based on maze routing algorithm,which integrates buffer insertion, buffer driving capability and topology generation, and can consider the general buffer insertion position to achieve robust clock skew control. It discusses an accurate timing analysis engine for estimating delay and slope, and a balanced routing scheme for better reducing offset during clock tree synthesis. It can perform active buffer insertion through buffer driving capability, and maintain accurate delay information and low offset. The experimental results show that the synthesis results not only satisfy the signal integrity constraints, but also maintain a reasonable skew.

关 键 词：集成电路设计 布线算法 时钟控制 缓冲器 驱动能力 

分 类 号：TN402[电子电信—微电子学与固体电子学]