关键工艺参数对高压SOI LDMOS击穿特性的影响研究  

Research on influence of key process parameters on breakdown characteristics of high voltage SOI LDMOS

作　　者：何晓斐 宋坤 赵杰[1,2] 孙有民 王英民[1,2] HE Xiaofei;SONG Kun;ZHAO jie;SUN Youmin;WANG Yingmin(Xi′an Microelectronic Technology Institute,Xi′an 710065,Shaanxi,China;Key Laboratory of Radiation Resistant Integrated Circuit Technology,Xi′an 710065,Shaanxi,China)

机构地区：[1]西安微电子技术研究所,陕西西安710065 [2]抗辐射集成电路技术重点实验室,陕西西安710065

出　　处：《微电子学与计算机》2022年第10期126-132,共7页Microelectronics & Computer

基　　金：装备预研基金项目(31513040204)。

摘　　要：本文基于顶层硅膜厚度为3μm的SOI衬底,设计了一种超薄硅层线性变掺杂漂移区结构的LDMOS晶体管,通过优化漂移区的工艺参数,显著改善了器件的表面电场分布,降低了漂移区两端的电场峰值,提高了横向耐压能力;通过形成超薄硅层漂移区提高了埋氧层处SiO_(2)与Si的临界击穿场强比,提升了器件的纵向耐压能力.采用分区掺杂的方式一次注入后高温扩散以形成漂移区线性分布,简化了工艺流程,对漂移区注入窗口进行了优化设计,实现了较好的漂移区浓度线性分布,通过先刻蚀再氧化的方式对漂移区进行减薄,降低了工艺要求.本文围绕关键工艺参数对器件击穿特性的影响进行了理论与仿真研究,对影响器件击穿电压的关键工艺参数进行了分析讨论,通过TCAD软件对器件工艺流程及特性参数进行了仿真分析,获得了优化的工艺条件.与同类高压器件相比,采用本文工艺结构的器件具有1036 V的高击穿电压,阈值电压为1.3 V,比导通电阻为291.9 mΩ·cm^(2).本文提出的器件所采用的SOI硅层厚度为3μm,易于与纵向NPN、高压CMOS器件兼容,为SOI高压BCD工艺集成的研究提供了参考.In this work,an improved LDMOS on SOI substrate is proposed with a varied lateral doping(VLD)drift region in an ultra thin silicon film.By optimizing the fabrication process of the drift region,the surface electric field peak is reduced,leading to an increase of the lateral breakdown voltage.The critical field ratio of SiO_(2) to Si is improved by forming an ultra thin drift region above the buried oxide,resulting in an enhanced vertical breakdown voltage.After one-time injection,high-temperature diffusion is adopted to form the linear distribution of the drift region,which simplifies the process flow.The injection window of the drift region is optimized to achieve a better linear distribution of the concentration of the drift region.The drift region is thinned by etching and then oxidation,which reduces the process requirements.This paper focuses on the theoretical and Simulation Research of the influence of key process parameters on the breakdown characteristics of devices,analyzes and discusses the key process parameters that affect the breakdown voltage of devices,simulates and analyzes the process flow and characteristic parameters of devices through TCAD software,and obtains the optimized process conditions.Compared with similar high-voltage devices,the device with this process structure has a high breakdown voltage of 1036V,the threshold voltage of the device is 1.3V,and the specific on resistance is 291.9mΩocm^(2).The thickness of SOI silicon layer used in the device proposed in this paper is 3μm.It is easy to be compatible with vertical NPN and high voltage CMOS devices,which provides a reference for the research of SOI high voltage BCD process integration.

关 键 词：绝缘体上硅 高压LDMOS 超薄漂移区 

分 类 号：TN386.1[电子电信—物理电子学]