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作 者:许家玮 武锦[2] 孔谋夫[1] 周磊[2] 季尔优 XU Jiawei;WU Jin;KONG Moufu;ZHOU Lei;JI Eryou(State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China,Chengdu 610054,China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China)
机构地区:[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054 [2]中国科学院微电子研究所,北京100029
出 处:《电子与封装》2022年第11期26-31,共6页Electronics & Packaging
摘 要:随着通信带宽的提升,系统对于数据采集带宽的要求逐渐升高。为了突破单通道数据采集芯片的性能瓶颈,时间交织技术越来越受到重视。介绍了一款基于时间交织技术的超宽带数据采集系统,阐述了数据采集系统中关键模块的构建原理。通过设计低抖动的4相位时钟产生模块、微变延时限模块与输入信号提取模块,实现了12 GSa/s 12 bit超宽带数据采集系统。测试结果表明,数据采集系统在10 MHz~2 GHz单音信号下的有效位数(ENOB)不低于7.2 bit,无杂散动态范围(SFDR)均在58 d B以上。宽带信号测试结果显示,其信噪比(SNR)达到30 d B,符合设计要求。With the improvement of communication bandwidth, the requirements of the system for data acquisition bandwidth are gradually increasing. In order to break the performance bottleneck of single channel data acquisition chip, time interleaving technology has attracted more and more attention. An ultra wideband(UWB) data acquisition system based on time interleaving technology is introduced, and the construction principle of the key modules of the data acquisition system is expounded. The 12 GSa/s 12 bit UWB data acquisition system is realized by designing a low jitter four phase clock generation module, a micro variable delay limit module and an input signal extraction module. The test results show that the effective number of bits(ENOB) of the data acquisition system under the single tone signal of 10 MHz-2 GHz is not less than 7.2 bit, and the spurious free dynamic range(SFDR) is more than 58 d B. The broadband signal test results show that the signal noise ratio(SNR) reaches 30 d B, which meets the design requirements.
关 键 词:数据采集系统 采样时间失配 FPGA 时间交织技术 时钟链路
分 类 号:TN492[电子电信—微电子学与固体电子学]
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