基于三维线性反馈移位寄存器的三维堆叠集成电路可重构测试方案  

Reconfigurable test scheme for 3D stacked integrated circuits based on 3D linear feedback shift register

作　　者：陈田[1,2] 鲁建勇 刘军[1,2] 梁华国[3] 鲁迎春 CHEN Tian;LU Jianyong;LIU Jun;LIANG Huaguo;LU Yingchun(School of Computer Science and Information Engineering,Hefei University of Technology,Hefei Anhui 230601,China;Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine(Hefei University of Technology),Hefei Anhui 230601,China;School of Microelectronics,Hefei University of Technology,Hefei Anhui 230601,China)

机构地区：[1]合肥工业大学计算机与信息学院,合肥230601 [2]情感计算与先进智能机器安徽省重点实验室(合肥工业大学),合肥230601 [3]合肥工业大学微电子学院,合肥230601

出　　处：《计算机应用》2023年第3期949-955,共7页journal of Computer Applications

基　　金：国家自然科学基金资助项目(62174048,62027815)。

摘　　要：三维堆叠集成电路(3D SIC)结构复杂,相较于二维集成电路(2D IC),设计有效的测试结构以降低测试成本更加困难。为降低3D SIC的测试成本,提出一种基于线性反馈移位寄存器(LFSR)的能够有效适应3D SIC不同测试阶段的三维LFSR(3D-LFSR)测试结构。3D-LFSR结构能够在堆叠前独立进行测试;在堆叠后,复用堆叠前的测试结构,并重构为一个适合当前待测电路的测试结构,且重构后的测试结构能进一步降低测试成本。基于3D-LFSR结构,设计了测试数据处理方法和测试流程,并采用混合测试模式以降低测试时间。实验结果表明,相较于双LFSR结构,3D-LFSR结构的平均功耗降低了40.19%,平均面积开销降低了21.31%,测试数据压缩率提升了5.22个百分点;相较于串行测试模式,采用混合测试模式的平均测试时间减少了20.49%。Due to complex structure of Three-Dimensional Stacked Integrated Circuit(3D SIC),it is more difficult to design an efficient test structure for it to reduce test cost than for Two-Dimensional Integrated Circuit(2D IC).For decreasing cost of 3D SIC testing,a Three-Dimensional Linear Feedback Shift Register(3D-LFSR)test structure was proposed based on Linear Feedback Shift Register(LFSR),which can effectively adapt to different test phases of 3D SIC.The structure was able to perform tests independently in the pre-stacking tests.After the stacking,the pre-stacking test structure was reused and reconfigured into a test structure suitable for the current circuit to be tested,and the reconfigured test structure was able to further reduce test cost.Based on this structure,the corresponding test data processing method and test flow were designed,and the mixed test mode was adopted to reduce the test time.Experimental results show that compared with the dual-LFSR structure,3D-LFSR structure has the average power consumption reduced by 40.19%,the average area overhead decreased by 21.31%,and the test data compression rate increased by 5.22 percentage points.And,using the hybrid test mode reduces the average test time by 20.49%compared to using the serial test mode.

关 键 词：三维堆叠集成电路 线性反馈移位寄存器 可测试性设计 可重构测试 测试成本 

分 类 号：TN47[电子电信—微电子学与固体电子学]