应用于时钟发生器的小数分频电路设计  

Design of Fractional Frequency Dividing Circuit Applied in Clock Generator

作　　者：张林寒 杨俊浩[2] 李小明[3] 秦战明 ZHANG Lin-han;YANG Jun-hao;LI Xiao-ming;QIN Zhan-ming(XIDIAN UNIVERSITY.Guangzhou institute of technology;China Electronics Technology Group Corporation 58 Research Institute;XIDIAN UNIVERSITY.School of Microelectronics)

机构地区：[1]西安电子科技大学广州研究院 [2]中国电子科技集团公司第58研究所 [3]西安电子科技大学微电子学院

出　　处：《中国集成电路》2023年第4期25-31,共7页China lntegrated Circuit

摘　　要：随着集成电路技术的迅猛发展,小数分频频率综合器已经广泛应用于通信系统中;芯片内对于时钟信号的稳定性以及分辨率的要求也越来越高,提高时钟信号的稳定性和分辨率是目前时钟发生器研究的重点。本文提出了一种高分辨率,高稳定性的小数分频器。首先依据延迟锁相环(DLL)实现小数分频的优势,提出了具有16位时钟输出的DLL结构,其次对比有源移相器实现相位内插的传统方法,提出了一种新型相位内插电路结构,最后结合数字算法控制单元控制DLL以及相位内插器电路,最终实现了输出稳定具有1/28分辨率的时钟信号。本设计采用中芯国际(SMIC)130nmCMOS工艺,电源电压为1.2V,输入信号时钟频率为200~400MHz。在200MHz输入频率下,整数分频为3,小数位为0.9375时,可实现对输入信号的3.9375分频,仿真输出平均分频为3.93778,频率误差在有限仿真时间和有限仿真精度内基本与设置的分频比基本一致。With the rapid development of integrated circuit technology,fractional frequency synthesizer has been widely used in communication systems;The requirements for the stability and resolution of the clock signal in the chip are also getting higher and higher.To improve the stability and resolution of the clock signal is the focus of the current clock generator research.This paper presents a high resolution,high stability fractional frequency divider.Firstly,according to the advantage of Delay Phase Locked Loop(DLL)in realizing fractional frequency division,a DLL structure with 16 bit clock output is proposed.Secondly,compared with the traditional method of active phase shifter to achieve phase interpolation,a new phase interpolation circuit structure is proposed.Finally,combined with the digital algorithm control unit to control the DLL and the phase interpolator circuit,a stable clock signal with 1/28 resolution is finally output.This design adopts SMIC 130nm CMOS process,the power supply voltage is 1.2V,and the input signal clock frequency is 200-400MHz.Under the input frequency of 200MHz,when the integer frequency division is 3 and the decimal place is 0.9375,3.9375 frequency division of the input signal can be achieved,and the average frequency division of the simulation output is 3.93778.The frequency error is basically consistent with the set frequency division ratio within the limited simulation time and limited simulation accuracy.

关 键 词：延迟锁相环 相位内插 小数分频 相位锁定 

分 类 号：TN74[电子电信—电路与系统] TN40