一种改进中值滤波算法的FPGA硬件实现  

Implementation of an improved median filtering algorithm based on FPGA

作　　者：程昊坤 和晓军 CHENG Haokun;HE Xiaojun(School of Automation and Electrical Engineering,Shenyang Ligong University,Shenyang,110159,China)

机构地区：[1]沈阳理工大学自动化与电气工程学院,辽宁沈阳110159

出　　处：《通信与信息技术》2023年第3期23-26,共4页Communication & Information Technology

摘　　要：针对传统中值滤波算法在混合噪声密度环境下对图像去噪处理效果不理想、耗费时间长不能满足实时性要求的问题,提出一种改进的中值滤波算法。将传统中值滤波排序后数组中的极大值、极小值取出赋予中值,并结合均值滤波对滤波窗口内像素值进行系数加权处理。增强了对受到椒盐和高斯混合噪声破坏图像的处理效果。同时将该算法用现场可编程逻辑门阵列(FPGA)实现,以满足不同应用场景中对于图像去噪实时性的需求。Aiming at the problems that the traditional median filtering algorithm is not ideal for image denoising processing in the mixed noise density environment,and it takes a long time to meet the real-time requirements,an improved median filtering algorithm is proposed.After sorting the traditional median filter,the maximum and minimum values in the array are taken out and assigned to the median value,and the pixel values in the filtering window are weighted by the coefficient combined with the mean filter.The image pro⁃cessing effect of salt/pepper and Gaussian mixture noise is enhanced.At the same time,the algorithm is implemented by field program⁃mable logic gate array(FPGA)to meet the real-time needs of image denoising in different application scenarios.

关 键 词：中值滤波 椒盐噪声 高斯噪声 混合噪声 现场可编程逻辑门阵列 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]