基于通用异步收发器的高速SerDes测试  

High-Speed SerDes Testing Based on Universal Asynchronous Transceiver

作　　者：柏娜[1,2] 朱非凡 许耀华[1,2] 王翊[1,2] 陈冬 BAI Na;ZHU Feifan;XU Yaohua;WANG Yi;CHEN Dong(Information Materials and Intelligent Sensing Laboratory of Anhui Province,Anhui University,Hefei 230601,China;Engineering Technology Research Center of Internet of Things Spectrum Sensing and Testing,Anhui University,Hefei 230601,China)

机构地区：[1]安徽大学信息材料与智能感知安徽省实验室,合肥230601 [2]安徽大学物联网频谱感知与测试工程技术研究中心,合肥230601

出　　处：《电子与封装》2023年第10期14-20,共7页Electronics & Packaging

摘　　要：提出了一种基于通用异步收发器(UART)的高速串行解串器(SerDes)的调试方法。由于SerDes在封装过程中管脚数量有限,难以把物理层(PHY)的测试点全部引出作为测试芯片的管脚。为了解决此问题,引入了UART模块作为PHY与外界通信的转换模块。针对待测的SerDes IP制定测试方案,此方案将UART等模块与待测IP级联,并通过UART模块将SerDes调试所需的配置参数传输到PHY的控制寄存器,从而在控制寄存器的控制下完成对PHY内部寄存器的读写操作。在1.25 Gbit/s、20 bit的工作模式下,完成对SerDes误码率的测试,实现了对SerDes芯片参数的动态调试,大大减少了测试复杂度和测试时间。An efficient high-speed serial deserialiser(SerDes)debugging method based on universal asynchronous transceiver(UART)is proposed.Due to the limited number of pins in the packaging process of SerDes,it is difficult to pin out all the test points of the physical layer(PHY)as the pins of the test chip.To solve this problem,the UART module is introduced as the conversion module for PHY communication with the outside world.A test plan is formulated for the SerDes IP to be tested,which cascades the UART and other modules with the IP to be tested,and transfers the configuration parameters required for SerDes debugging to PHY's control register through the UART module,so as to complete the reading and writing operations of PHY's internal registers under the control of the control register.In the operating mode of 1.25 Gbit/s and 20 bit,the testing of SerDes bit error rate is completed,and dynamic debugging of SerDes chip parameters is realized,which greatly reduce the testing complexity and time.

关 键 词：串行解串器 通用异步收发器 环回功能 误码率 内建自测试 

分 类 号：TN407[电子电信—微电子学与固体电子学]