基于16 nm FinFET工艺FPGA的低功耗PCIe Gen3性能研究  

Research on Low-Power PCIe Gen3 Performance Based on 16 nm FinFET Process FPGA

作　　者：季振凯 杨茂林 于治 JI Zhenkai;YANG Maolin;YU Zhi(East Technology,Inc.,Wuxi 214072,China)

机构地区：[1]无锡中微亿芯有限公司,江苏无锡214072

出　　处：《电子与封装》2023年第11期54-61,共8页Electronics & Packaging

摘　　要：大数据时代对高速总线的高带宽、低延时及高灵活性有更苛刻的要求,高速串行总线(PCIe)与FPGA的集成能够满足新兴领域的需求,但需要对其在高温和低温下的性能稳定性及低功耗性进行探究。以16 nm FinFET工艺SRAM型FPGA为对象,搭建针对低功耗PCIe第三代(Gen3)的高速通信的性能测试、温升测试以及高温及低温功耗测试方案。测试结果表明,在通信过程中被测电路与CPU通信稳定,读、写速率分别可达3907 MB/s、4430 MB/s,达到理论最大带宽的54.1%、61.4%;被测电路温升不显著,常温下电路的表面温度比对照电路低18.4%;其在高温125℃下的功耗比对照电路低41.9%。该工艺下的电路能够稳定运行PCIe Gen3总线,并在低功耗、低发热状态下实现高质量的信号传输。In the era of big data,there are more stringent requirements for high-speed buses with high bandwidth,low latency and high flexibility.The integration of peripheral component interconnect express(PCIe)with FPGA can meet the needs of emerging fields,but its performance of stability and low-power consumption at the high temperature and low temperature need to be explored.Focusing on the SRAM FPGA using 16 nm FinFET technology,a scheme of performance test,temperature rise test,and power consumption test at the high temperature and low temperature for high-speed communication of low-power PCIe generation 3(Gen3)is built.The test results show that the communication between the tested circuit and the CPU is stable during the communication process,and the read rate and write rate can reach 3907 MB/s and 4430 MB/s,respectively,reaching 54.1%and 61.4%of the theoretical maximum bandwidth;the temperature rise of the tested circuit is not significant,and the surface temperature of the circuit at room temperature is 18.4%lower than that of the control device;its power consumption at the high temperature of 125℃is 41.9%lower than that of the control device.The circuit under this process can operate the PCIe Gen3 bus stably and achieve high-quality signal transmission in a low-power and low heating state.

关 键 词：FINFET SRAM型FPGA PCIe Gen3 低功耗 

分 类 号：TN47[电子电信—微电子学与固体电子学]