基于新型部分积生成器和提前压缩器的乘法器设计  

Multiplier Design Based on a New Partial Product Generator and Advance Compressor

作　　者：蔡永祺 李振涛 万江华 CAI Yongqi;LI Zhentao;WAN Jianghua(School of Physics and Optoelectronics,Xiangtan University,Xiangtan 411000,China;Hunan Great-Leo Microelectronics Co.,Ltd.,Changsha 410000,China)

机构地区：[1]湘潭大学物理与光电工程学院,湖南湘潭411100 [2]湖南毂梁微电子有限公司,长沙410000

出　　处：《电子与封装》2023年第11期87-92,共6页Electronics & Packaging

摘　　要：为了提高乘法器性能,采用基4 Booth编码算法设计Booth编码器,使用华莱士树压缩结构设计16 bit有符号数乘法器;针对部分积生成的复杂过程提出一种新的部分积生成器,同时进行部分积的产生与选择,提高了部分积生成效率;针对压缩过程中的资源浪费,提出一种部分积提前压缩器,将某几位部分积在进入压缩树之前进行合并,减少了压缩单元的使用。基于28 nm工艺对乘法器进行逻辑综合,关键路径延时为0.77 ns,总面积为937.3μm2,功耗为935.71μW,能够较好地提升乘法器的面积利用率和运算性能。In order to improve the performance of the multiplier,a Booth encoder is designed by using the Radix 4 Booth encoding algorithm,and a signed 16 bit multiplier is designed by using the Wallace tree compression structure.A new partial product generator is proposed for the complex process of partial product generation,which simultaneously generates and selects the partial products,and improves the efficiency of the partial product generation.For the waste of resources in the compression process,a partial product advance compressor is proposed to merge certain partial products before entering the compressed tree,reducing the use of compression units.The multiplier logic synthesis is based on 28 nm process.The critical path delay is 0.77 ns,the total area is 937.3μm2,and the power consumption is 935.71μW,which can better improve the area utilization and computing performance of the multiplier.

关 键 词：乘法器 BOOTH编码 部分积 压缩器 

分 类 号：TN403[电子电信—微电子学与固体电子学]