JFET区宽度对SiC MOSFET单粒子效应的影响  

Impact of JFET Region Width on Single Event Effects of SiC MOSFETs

作　　者：许明康 贾云鹏 周新田 胡冬青 吴郁 唐蕴 黎荣佳 赵元富 王亮 XU Mingkang;JIA Yunpeng;ZHOU Xintian;HU Dongqing;WU Yu;TANG Yun;LI Rongjia;ZHAO Yuanfu;WANG Liang(Faculty of Information Technology,Beijing University of Technology,Beijing 100124,China;Beijing Microelectronics Technology Institute,Beijing 100076,China)

机构地区：[1]北京工业大学信息学部,北京100124 [2]北京微电子技术研究所,北京100076

出　　处：《原子能科学技术》2023年第12期2295-2303,共9页Atomic Energy Science and Technology

基　　金：国家自然科学基金(62204011)。

摘　　要：SiC MOSFET(金属-氧化物半导体场效应晶体管)关键参数——结型场效应晶体管(JFET)区宽度一直被认为是SiC MOSFET单粒子效应的主要影响因素。针对这一影响因素,以同一结构不同JFET区宽度的1.2 kV SiC MOSFET器件为对象进行单粒子效应实验,探究JFET区宽度对器件单粒子烧毁阈值电压、漏电退化阈值电压以及负栅压条件下器件性能的影响。结果表明:随着JFET区宽度的减小,漏电退化阈值电压增大;减小器件JFET区宽度可有效改善器件的抗单粒子效应能力;在负栅压条件下对器件单粒子效应也会有此效果。采用Sentaurus TCAD进行模拟仿真,模拟结果证实,JFET区宽度以及负栅压的变化会影响氧化层下JFET区内空穴的积累,随之影响氧化层电场强度,从而影响器件单粒子漏电退化,与实验结果相符。以上结果为SiC MOSFET抗单粒子效应加固提供了理论基础。The advantages of SiC MOSFETs(metal-oxide semiconductor field effect transistor)make this technology attractive for space,avionics and high-energy accelerator applications.However,the current commercial technologies are still susceptible to single event effects(SEEs)and latent damages induced by the radiation environment.In commercial SiC MOSFETs exposed to heavy ions,two types of latent damages were experimentally observed.One type is observed at bias voltages just below the degradation onset voltage and involves the gate oxide.The other type of damage was observed at bias voltages below the single event burnout(SEB)limit and which was attributed to changes in the silicon carbide lattice.The key parameter of SiC MOSFET,JFET region width,has been considered as the main influence factor of SEEs of SiC MOSFET.Aiming at this influence factor,SEE experiment was carried out on 1.2 kV SiC MOSFET devices with different JFET region widths of the same structure to investigate the influence of different JFET region widths on the device’s SEEs burning threshold voltage,leakage degradation threshold voltage,and the device performance under negative gate voltage conditions,and the test results show that the leakage degradation threshold voltage increases with the decrease of the JFET region width.Reducing the JFET region width of the device can effectively improve the SEEs resistance of the device,this effect is also observed under negative gate voltage bias conditions.Under negative gate voltage bias conditions,the effect of JFET region width on the SEEs of the device is reduced by the negative gate voltage.Sentaurus TCAD is used for simulation,and the simulation results confirm that the JFET region width and the negative gate voltage bias affect the accumulation of holes in the JFET region under the oxide layer,which in turn affects the oxide layer field strength,and thus affects the single event leakage degradation of the device.It is also demonstrated that SEB is caused by a localized energy pulse due to ion collisional

关 键 词：碳化硅 漏电退化 单粒子效应 抗辐照 

分 类 号：TL99[核科学技术—核技术及应用] TN386.1[电子电信—物理电子学] TN306