160Msps双通道时间交织的采样保持电路设计  

Design of 160Msps Dual Channel and Time-interleaved Sample and Hold Circuit

作　　者：汪杰 谢亮 WANG Jie;XIE Liang(School of Physics and Optoelectronics,Xiangtan University,Hunan,411105,China;Hunan Engineering Laboratory for Microelectronics,Optoelectronics and System on A Chip,Hunan,411105,China.)

机构地区：[1]湘潭大学物理与光电工程学院,湖南411105 [2]微光电与系统集成湖南省工程实验室,湖南411105

出　　处：《集成电路应用》2023年第11期1-3,共3页Application of IC

摘　　要：阐述一种双通道时间交织采样保持电路的设计,它是基于电源电压3.3V,0.13μm CMOS工艺,应用于12位160Msps双通道时间交织流水线模数转换器(ADC)中,改善型栅压自举开关被设计用来实现高的线性度。仿真结果表明,当采样速率为160Msps时,有效位数达到14.86bit,电源电流为17.3mA,无杂散动态范围达到96.2dB。This paper expounds a dual channel time-interleaved sample-and-hold circuit for a 12bit,160Msps time-interleaved pipeline ADC under 3.3V supply voltage.It is fabricated in 0.13μm CMOS process.To improve the linearity in the sample-and-hold circuit a bootstrapped switch is used.The simulation result shows that the sample-and-hold circuit has an ENOB of 14.86bit,a current supply of 17.3mA and an SFDR of 96.2dB at a sampling rate of 160Msps.

关 键 词：采样保持电路 ADC 时间交织 栅压自举开关 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN792