7~13 GHz宽带高效率驱动放大器设计  

Design of 7 ~ 13 GHz Broadband High-efficiency Driver Amplifier

作　　者：豆兴昆 李彬 谭小媛 蒋乐 叶坤 DOU Xingkun;LI Bin;TAN Xiaoyuan;JIANG Le;YE Kun(China Key System&Integrated Circuit Co.,Ltd.,Wuxi 214000,China)

机构地区：[1]中科芯集成电路有限公司,江苏无锡214000

出　　处：《现代信息科技》2024年第5期73-76,80,共5页Modern Information Technology

摘　　要：基于0.25μm GaAs PHEMT工艺设计了一款7~13 GHz微波单片高效率驱动放大器。芯片采用两级级联拓扑结构,在输入级引入共源并联负反馈结构拓宽工作带宽,同时为兼顾输出功率和效率,在输出级引入等效RC模型拟合输出管芯的最优阻抗。基于等效RC模型,通过采用电抗匹配方式降低输出宽带匹配网络的损耗来实现较高的输出功率和附加效率。实测与仿真曲线吻合度较好,实测结果显示:在7~13 GHz工作带宽范围内,输入驻波比小于1.5,输出驻波比小于1.8,线性增益大于13 d B,3 d B压缩点输出功率大于24 d Bm,功率附加效率大于35%,芯片面积为1.8 mm×0.8 mm。A 7~13 GHz microwave monolithic high-efficiency driver amplifier based on 0.25μm GaAs PHEMT process is designed.The chip uses a two-stage cascade topology,introduces a common source parallel negative feedback structure in the input stage to broaden the working bandwidth.In order to take into account both the output power and efficiency in the output stage,an equivalent RC model is introduced to fit the optimal impedance of the output transistor.Based on the equivalent RC model,high output power and power added efficiency are achieved by using a reactance matching topology to reduce the loss of the output broadband matching network.The simulation curves agree well with the measured curves,and test results show that during the bandwidth from 7 to 13 GHz,the input VSWR is less than 1.5,the output VSWR is less than 1.8,the linear gain is more than 13 dB,the 3 dB compression point output power is greater than 24 dBm,and the power added efficiency is higher than 35%,and the chip area is 1.8 mm×0.8 mm.

关 键 词：砷化镓 微波单片集成电路 驱动放大器 功率附加效率 并联负反馈 阻抗匹配 

分 类 号：TN722[电子电信—电路与系统]