SoC芯片扫描链测试设计与实现  

Design and Implementation of Scanning Chain Testing for SoC Chips

作　　者：卢叶青 LU Yeqing(School of Information and Communication Engineering,North Central University,Shanxi 030051,China)

机构地区：[1]中北大学信息与通信工程学院,山西030051

出　　处：《集成电路应用》2024年第3期52-53,共2页Application of IC

摘　　要：阐述针对SoC芯片,进行压缩测试、stuck-at测试和全速测试的设计,并通过Tessent软件插入扫描链和生成ATPG自动测试向量。结果表明,芯片固定型故障、时延相关故障的覆盖率满足测试要求。This paper describes the design of compression testing,stuck at testing,and full speed testing for SoC chips,and uses Tessant software to insert scan chains and generate ATPG automatic test vectors.The results indicate that the coverage of fixed chip faults and delay related faults meets the testing requirements.

关 键 词：集成电路 可测试性设计 扫描链测试 EDT电路 

分 类 号：TN407[电子电信—微电子学与固体电子学]