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作 者:谭玥 杜永乾 李桂芳 刘诗斌[1] TAN Yue;DU Yongqian;LI Guifang;LIU Shibin(School of Electronics and Information,Northwestern Polytechnical University,Xi’an 710072,China;Shenzhen Research Institute of Northwestern Polytechnical University,Shenzhen 518057,Guangdong China)
机构地区:[1]西北工业大学电子信息学院,陕西西安710072 [2]西北工业大学深圳研究院,广东深圳518057
出 处:《华中科技大学学报(自然科学版)》2024年第3期20-27,共8页Journal of Huazhong University of Science and Technology(Natural Science Edition)
基 金:陕西省自然科学基础研究计划资助项目(2020JQ-206);深圳市科技创新委员会基金知识创新基础研究(自由探索)项目(JCYJ20180306171040865);国家自然科学基金资助项目(61873209,61504107,61704139)。
摘 要:使用Verilog-A硬件描述语言对自旋转移矩磁随机存储器(STT-MRAM)的基本存储单元磁隧道结(MTJ)器件进行建模,采用Cadence软件对模型进行验证.基于已建立的MTJ模型设计STT-MRAM的读写电路.针对写入延迟过长的问题,对传统写入电路进行改进,通过增加写入支路上晶体管的数量来增加写入电流及降低基本存储单元(1T1MTJ)结构中晶体管的压降,有效地缩短了磁隧道结翻转过程的开关延迟时间,提高了写入驱动电路的工作速度;读取电路采用改进的三稳态传输结构,降低了电路功耗,提高了读取数据的准确性.最后设计实现了1Kb的STT-MRAM的非易性存储,仿真结果表明所设计的STT-MRAM能够实现数据的存取过程.Verilog-A hardware description language was adopted to model the magnetic tunnel junction(MTJ)device which is the basic storage unit of spin transfer torque magnetic random access memory(STT-MRAM).Cadence software was adopted to verify this model.The read-write circuit of STT-MRAM was designed based on the established model.Aiming at the problem of excessive write delay,the traditional write circuit was improved.The switching delay time of MTJ reversal process was effectively shortened and the working speed of the write drive circuit was improved by increasing the number of transistors on the write branch to increase the write current and reduce the voltage drop of transistors in the structure of basic storage unit(1T1MTJ).An improved tri-stable transmission structure was adopted in read circuit,which reduces the power consumption and improves the accuracy of reading data.Finally,the non-volatile storage of 1Kb STT-MRAM was designed and implemented.The simulation results show that the designed STT-MRAM can realize the data storage and reading and writing process.
关 键 词:磁存储器 非易失性存储器 自旋转移矩 磁隧道结 可靠性读写电路
分 类 号:TN4[电子电信—微电子学与固体电子学]
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