基于寄生电感优化的分立器件布局方法研究  

Research on discrete device layout method based on parasitic inductance optimization

作　　者：张杰[1,2,3] 陈怡飞[1,2] 余柳峰 谢卫冲 江路 ZHANG Jie;CHEN Yifei;YU Liufeng;XIE Weichong;JIANG Lu(Hubei University of Technology,Key Laboratory of Solar Energy Efficient Utilization and Energy Storage Operation Control in Hubei Province,Wuhan 430068,China;Hubei University of Technology,College of Electrical and Electronic Engineering,Wuhan 430068,China;Xiangyang Industrial Institute of Hubei University of Technology,Xiangyang 441100,Hubei China)

机构地区：[1]湖北工业大学电气与电子工程学院,武汉430068 [2]湖北工业大学太阳能高效利用及储能运行控制湖北省重点实验室,武汉430068 [3]襄阳湖北工业大学产业研究院,湖北襄阳441100

出　　处：《中南民族大学学报（自然科学版）》2024年第4期547-553,共7页Journal of South-Central University for Nationalities：Natural Science Edition

基　　金：湖北省重点研发计划资助项目(2020BBB084)。

摘　　要：为了探究分立器件与PCB组合形成的半桥电路时采用何种布局方式才能尽最大限度减小线路寄生电感的问题,基于换流回路寄生电感概念,提出了一种经优化的分立器件在PCB上的布局方式,进而减小换流回路的寄生电感,随后通过有限元仿真软件评估并验证不同布局方式所产生的寄生电感,并结合LTspice电路仿真软件评估不同布局方式对器件电开关特性的影响,最后通过双脉冲实验验证了所设计的一种经过优化布局半桥电路的优越性.所提供的半桥电路的设计方法为分立器件在PCB上的布局提供了理论和技术支撑.In order to explore the layout method used to minimize parasitic inductance in a half bridge circuit formed by combining discrete devices and PCBs,an optimized layout method for discrete devices on PCB based on the concept of parasitic inductance in the commutation circuit is proposed.Subsequently,finite element simulation software is used to evaluate and verify the parasitic inductance generated by different layout methods,and combined with LTspice circuit simulation software to evaluate the differences in voltage stress and switching losses of switching devices caused by different layout methods.Finally,the superiority of the optimized layout half bridge circuit designed was verified through double pulse experiments.The design method of the half bridge circuit provided provides theoretical and technical support for the layout of discrete devices on PCBs.

关 键 词：分立器件 半桥电路 寄生电感 有限元仿真 

分 类 号：TN386.1[电子电信—物理电子学]