32 nm工艺下基于输入分离C单元的三节点翻转容忍锁存器设计  

Triple-node Upset Tolerant Latch Design Based on Input-separated C-element in 32 nm Process

作　　者：夏宇 XIA Yu(School of Computer Science and Engineering,Anhui University of Science and Technology,Huainan 232001,China)

机构地区：[1]安徽理工大学计算机科学与工程学院,安徽淮南232001

出　　处：《现代信息科技》2024年第9期43-46,52,共5页Modern Information Technology

摘　　要：随着集成电路特征尺寸的不断缩减,存储电路中单粒子效应造成的多节点翻转的概率越来越大,严重影响了电路的可靠性。因此,为了增加存储电路的抗辐射加固能力和可靠性,提出一种三节点翻转加固锁存器TNUTL。该锁存器使用双模冗余和输入分离C单元实现100%三节点翻转容忍能力。钟控技术和传输门的使用有效降低了锁存器的功耗和延迟。32 nm CMOS工艺下的仿真结果表明,所提出的锁存器对比同类型结构平均降低了36.84%的功耗和65.31%的延迟,以及82.13%的功耗延迟积。As the feature size of integrated circuits continues to decrease,the probability of multi-node upset due to single particle effect in storage circuits is increasing,which seriously affects the reliability of the circuits.Therefore,to increase the radiation hardening capability and reliability of the circuit,a triple-node upset hardened latch,TNUTL,is proposed.The latch uses dual-mode redundancy and input separated C-element to achieve 100%triple-node upset tolerance.The use of clocking techniques and transmission gates effectively reduces the power consumption and delay of the latch.The simulation results under 32 nm CMOS process show that the proposed latch reduces power consumption by 36.84%and delay by 65.31%on average as well as power-delay product by 82.13%as compared to the same type of structure.

关 键 词：锁存器 C单元 软错误 三节点翻转 

分 类 号：TN43[电子电信—微电子学与固体电子学] TP302.8[自动化与计算机技术—计算机系统结构]