先进封装Chiplet技术  

Advanced Packaging Chiplet Technology

作　　者：吴蝶 WU Die(School of Management,Shanghai University of Engineering Science,Shanghai 201620)

机构地区：[1]上海工程技术大学管理学院,上海201620

出　　处：《软件》2024年第4期154-156,180,共4页Software

基　　金：上海市2023年度决策咨询研究产业和信息化专项课题“推动上海市集成电路领域Chiplet创新发展的策略研究”(2023-Z-C02)。

摘　　要：随着先进制程技术迭代到5nm、3nm,摩尔定律的效应逐渐趋缓,制程开发成本和复杂度也在不断攀升。在芯片散热、传输带宽、制造良率等面临挑战的背景下,单颗芯片的性能提升遇到了“功耗墙、存储墙、面积墙”等瓶颈。而Chiplet技术的出现,为这一问题提供了新的解决思路。本文概述Chiplet芯片的底层封装技术,阐述我国先进封装领域发展的现状,对我国先进封装发展提出建议。As advanced process technology iterates to 5nm and 3nm,the effect of Moore's Law gradually slows down,and the cost and complexity of process development continue to rise.In the background of challenges such as chip cooling,transmission bandwidth and manufacturing yield,the performance improvement of a single chip has encountered bottlenecks such as"power consumption walls","storage walls"and"area walls".The emergence of Chiplet technology provides new solutions to this problem.This article provides an overview of the underlying packaging technology of Chiplet chips,elaborates on the current development status of advanced packaging in China,and puts forward suggestions for the development of advanced packaging in China.

关 键 词：Chiplet 2.5D封装 3D封装 先进封装 

分 类 号：TN40[电子电信—微电子学与固体电子学]