一种低开销的三节点翻转容忍锁存器设计  

Design of a Low-Cost Triple-Node-Upsettolerant Latch

作　　者：秦学伟 QIN Xuewei(School of Computer Science and Engineering,Anhui University of Science and Technology,Huainan 232001,China)

机构地区：[1]安徽理工大学计算机科学与工程学院,安徽淮南232001

出　　处：《河南科技》2024年第8期9-13,共5页Henan Science and Technology

摘　　要：【目的】随着半导体技术的发展,集成电路特征尺寸不断缩小,导致其对软错误更加敏感,因此需要对集成电路存储单元进行加固。【方法】使用Hspice进行实验与仿真,基于PTM32nm CMOS工艺,提出了一种低开销的三节点翻转容忍锁存器结构。【结果】该锁存器包含2个单节点自恢复模块、1个二级错误拦截模块、3个传输门。每个自恢复模块由1个施密特触发器和1个钟控的施密特触发器组成,首尾相连形成环形结构,有效地实现了三节点翻转的容忍。【结论】仿真结果表明:与现有的其他功能相同的锁存器相比,所提出的锁存器具有完整的三节点容忍能力,并且将功耗、延迟、面积、功率延迟积分别降低了约37.58%、41.25%、27.77%、75.83%。[Purposes]With the development of semiconductor technology,the shrinking feature size of integrated circuits has made them more sensitive to soft errors,necessitating reinforcement of the storage units in integrated circuits.[Methods]Experiments and simulations were conducted using Hspice.Based on the PTM32nm CMOS process,a low-cost triple node upsets tolerant latch(LTNTL)structure was proposed.[Findings]The latch consists of 2 single-node self-recovery modules,1 secondary error interception module,and 3 transmission gates.Each self-recovery module consists of a Schmitt trigger and a clock-gating Schmitt trigger connected in a loop structure,effectively achieving tolerance to TNU.[Conclusions]Simulation results demonstrate that compared to other latches with same functions,the proposed latch has complete TNU tolerance capability and reduces power consumption,delay,area,and power-delay product by approximately 37.58%,41.25%,27.77%,and 75.83%,respectively.

关 键 词：锁存器 软错误 三节点翻转 

分 类 号：TN47[电子电信—微电子学与固体电子学]