低功耗非易失性存储器存储单元及存储芯片架构  

The architecture and bit cell of low power non-volatile memory

作　　者：王浩 郭术明 聂筱敏 WANG Hao;GUO Shu-ming;NIE Xiao-min(Shanghai Branch,CSMC technologies Corporation)

机构地区：[1]无锡华润上华科技有限公司上海分公司

出　　处：《中国集成电路》2024年第6期37-42,55,共7页China lntegrated Circuit

摘　　要：基于传统的0.18um单栅Logic CMOS工艺实现超低功耗非易失性存储器芯片的设计与验证,该存储芯片采用差分结构单元,无需增加光罩,利用双向的F-N隧穿原理进行编程擦除机理,可实现EEPROM功能。最终的测试结果显示该芯片具有超低的待机、编程和读取功耗,读取速度最高达100MHz,Cycling可达100K,且具有非常优秀的数据保持能力,非常适用于低成本低功耗的应用场景。A low power non-volatile memory is designed and verified on a traditional 0.18um single-gate CMOS process.This memory utilizes a differential structure cell and employs bidirectional F-N tunneling for programming and erasing mechanisms,enabling EEPROM functionality without the need for additional masks.The final test results of the chip demonstrate that the chip has ultra-low standby,programming,and read power consumption.The maximum read speed can reach 100MHz.It can achieve 100K cycling and exhibits excellent data retention capabilities.This makes it a strong contender in the market for low-power non-volatile memory.

关 键 词：CMOS工艺 低功耗 非易失性存储器 双向F-N隧穿 数据保持 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]