用于LLC谐振拓扑的PFM发生器IP核设计  

Design on PFM Generator IP Core for LLC Resonant Topology

作　　者：芮天喆 曾庆立[1] RUI Tianzhe;ZENG Qingli(School of Communication and Electronic Engineering,Jishou University,Jishou Hunan 416000,China)

机构地区：[1]吉首大学通信与电子工程学院,湖南416000

出　　处：《集成电路应用》2024年第4期10-12,共3页Application of IC

摘　　要：阐述LLC谐振拓扑的结构和频率特性,针对LLC谐振变换器对占空比固定为50%、频率可调节的需求,基于国产Seal 5000系列SA5Z-30-D1平台,提出一种带死区和互补输出的PFM发生器IP核。提出的IP核内部具有上下计数模式计数器和死区与互补生成模块,通过寄存器设置计数器最大值与自增量,以计数器方向信号作为PFM输出送入死区与互补生成模块,在死区与互补生成模块中产生反相信号并插入死区。通过示波器观测实际输出信号表明该IP核输出效果良好,可以灵活地输出可配置的带有死区、互补输出的PFM波形。This paper describes the structure and frequency characteristics of the LLC resonant topology,and a PFM generator IP core with dead-time and complementary outputs is proposed based on the domestic Seal 5000 series SA5Z-30-D1 platform to meet the demand of the LLC resonant converter for a fixed duty cycle of 50%and adjustable frequency.The proposed IP core has an up-down counting mode counter and a dead-time and complementary generation module.The maximum value and increment of the counter are set through registers,and the direction signal of the counter is fed into the dead-time and complementary generation module as the PFM output,and the inverse signals are generated and inserted into the dead-time in the dead-time and complementary generation module.Observation of the actual output signals through an oscilloscope shows that the IP core outputs good results and can flexibly output configurable PFM waveforms with dead-time and complementary outputs.

关 键 词：集成电路 PFM FPGA IP核 

分 类 号：TN791[电子电信—电路与系统]