具有阶梯掺杂缓冲层的双栅超结LDMOS  

Dual-gate superjunction LDMOS with step-doped buffer layer

作　　者：唐盼盼 张峻铭 南敬昌[1] TANG Panpan;ZHANG Junming;NAN Jingchang(School of Electronics and Information Engineering,Liaoning Technical University,Huludao 125105,Liaoning Province,China)

机构地区：[1]辽宁工程技术大学电子与信息工程学院,辽宁葫芦岛125105

出　　处：《电子元件与材料》2024年第5期505-512,共8页Electronic Components And Materials

基　　金：国家自然科学基金(61971210)。

摘　　要：具有N型缓冲层的超结横向双扩散金属-半导体场效应晶体管(SJ-LDMOS)结构能够有效抑制传统结构中存在的衬底辅助耗尽效应(SAD)。为进一步优化器件性能,提出了一种具有阶梯型掺杂缓冲层的双栅极SOI基SJ-LDMOS(DG SDB SJ-LDMOS)器件结构。该结构采用沟槽栅极与平面栅极相互结合的形式,在器件内形成两条电流传导路径,其一通过SJ结构中高掺杂的N型区传输,另一条则通过阶梯掺杂缓冲层传输,同时阶梯掺杂缓冲层可以进一步改善表面电场分布,提高器件的耐压。双导通路径提高了SJ层和阶梯掺杂缓冲层的正向电流均匀性,从而有效地降低了器件的导通电阻。仿真结果表明:所提出的器件结构可实现394 V的高击穿电压和10.11 mΩ·cm^(2)的极低比导通电阻,品质因数达到了15.35 MW/cm^(2),与具有相同漂移区长度的SJ-LDMOS相比击穿电压提高了47%,比导通电阻降低了64.8%。The structure of super-junction lateral double-diffused metal-oxide-semiconductor(SJ-LDMOS)field-effect transistor with an N-type buffer layer can effectively suppress the substrate-assisted depletion(SAD)effect in traditional structures.To further optimize device performance,a dual-gate silicon-on-insulator(SOI)-based SJ-LDMOS(DG SDB SJ-LDMOS)device structure was proposed with a step-doped buffer layer.The device contains not only planar gate but also trench gate,which could create two current conduction paths within the device.One path is through the highly doped N-type region in the SJ structure,while the other is through the step-doped buffer layer.Additionally,the stepped doping buffer layer can further improve the surface electric field distribution and enhance the devices breakdown voltage.The dual conduction paths improve the uniformity of forward current in the SJ layer and the stepped doping buffer layer,which could effectively reduce the on-state resistance of the device.The simulation results demonstrate that the proposed device structure can achieve a high breakdown voltage of 394 V,an extremely low specific on-resistance of 10.11 mΩ·cm^(2),and a resultant FOM value of 15.35 MW/cm^(2).Additionally,the results represent a significant improvement compared to the SJ-LDMOS devices.With the same drift region length,the breakdown voltage is increased by 47%,and the specific on-resistance is decreased by 64.8%.

关 键 词：SJ-LDMOS 阶梯掺杂 沟槽栅极 击穿电压 比导通电阻 

分 类 号：TN386.1[电子电信—物理电子学]