优化目标检测网络的设计与FPGA硬件实现  

Optimized object detection network design and FPGA hardware implementation

作　　者：谢锋[1] 杨昶楠 陆军 XIE Feng;YANG Changnan;LU Jun(School of Computer,Electronics and Information,Guangxi University,Nanning 530004,China;Propaganda Department of the Party Committee,Nanning College for Vocational Technology,Nanning 530008,China)

机构地区：[1]广西大学计算机与电子信息学院,广西南宁530004 [2]南宁职业技术学院党委宣传部,广西南宁530008

出　　处：《广西大学学报（自然科学版）》2024年第3期595-605,共11页Journal of Guangxi University（Natural Science Edition）

基　　金：广西创新驱动重大专项(2020AA24002AA)。

摘　　要：针对目标检测算法受限于越来越严苛的硬件算力与存储,导致在小型化设备上的部署存在巨大困难,本文提出一种基于现场可编程门阵列(FPGA)的深度学习模型专用加速器方案来实现目标检测的边缘部署。通过优化原始模型的卷积算子并进行剪枝和量化,使参数量减少52%。移植在MLK-F20-CM02-3EG开发板上的实验表明,特制化的加速器理论算力峰值达到407 GOPS,实际算力达328 GOPS,数字信号处理器(DSP)使用率为64%,在边缘设备上的功耗相比图形处理器大型平台降低了98%。Addressing the challenge of target detection algorithms being constrained by increasingly stringent hardware power and storage requirements,which pose significant difficulties in deploying on miniature devices,this paper propoded a dedicated accelerator solution for deep learning models based on field programmable gate arrays(FPGA)to achieve edge deployment of target detection.By optimizing the convolutional operators of the original model and performing pruning and quantization,the parameter count was reduced by 52%.Experiments conducted on the MLK-F20-CM02-3EG development board found that the specialized accelerator achieved a theoretical peak performance of 407 GOPS and an actual performance of 328 GOPS,with a digital signal processor(DSP)utilization rate of 64%,and the power consumption on edge devices was 98%lower compared to large GPU platforms.

关 键 词：目标检测 现场可编程门阵列加速 卷积算子优化 剪枝 量化 特制加速器 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]