R-DSP中二级Cache控制器的优化设计  

Optimization Design of Secondary Cache Controller in R-DSP

作　　者：谭露露 谭勋琼[1] 白创 TAN Lulu;TAN Xunqiong;BAI Chuang(School of Physics&Electronic Science,Changsha University of Science&Technology,Changsha 410000,China)

机构地区：[1]长沙理工大学物理与电子科学学院,长沙410000

出　　处：《电子与封装》2024年第7期63-68,共6页Electronics & Packaging

基　　金：湖南省教育厅优秀青年科研项目(22B0287)。

摘　　要：针对二级Cache控制器(L2)对于提升R数字信号处理器(R-DSP)访存效率和整体性能的重要作用,结合L2中涉及的内存安全维护和多请求访存仲裁问题,在现有R-DSP中L2基础上实现优化。首先,采用多重分块的存储组织结构,提高访存效率;其次,并行处理一级Cache控制器请求与外存请求,减小请求处理周期;最后,增加带宽管理与存储保护功能,合理仲裁访存请求并维护存储安全。实验结果表明,相较于传统设计,新设计在保护二级存储安全的同时实现带宽管理式访存仲裁。与现有R-DSP中的L2相比,新设计的存储体单拍最大可响应访存请求数量提升了1倍,一级请求和外存请求的平均处理时钟周期数分别降低了25%和19.6%。Aiming at the important role of the secondary cache controller(L2)for improving the access efficiency and overall performance of R-DSP,and combining the memory security maintenance and multi-request access arbitration involved in the L2,the following optimizations are implemented on the basis of the L2 in the existing R-DSP.Firstly,the multi-block storage organization structure is adopted to improve the efficiency of memory access.Secondly,the first-level cache controller requests and external memory requests are processed in parallel to reduce the request processing cycle.Finally,bandwidth management and storage protection functions are added to reasonably arbitrate memory access requests and maintain storage security.Experimental results show that compared with the traditional design,the new design realizes bandwidth management access arbitration while protecting the security of secondary storage.Compared with L2 in the existing R-DSP,the maximum number of memory access requests that can be responded to in a single beat of the new design is increased by 100%,and the average processing clock cycles of first-level requests and external memory requests are reduced by 25%and 19.6%respectively.

关 键 词：DSP 二级CACHE 存储结构 并行处理 存储保护 带宽管理 

分 类 号：TN47[电子电信—微电子学与固体电子学] TP333.5[自动化与计算机技术—计算机系统结构]