基于0.18μm CMOS工艺的低功耗采样保持电路  

Low Power Sample-and-hold Circuit Based on 0.18 μm CMOS Process

作　　者：韩昌霖 丁浩 吴建飞 HAN Changlin;DING Hao;WU Jianfei(College of Electronic Science,National University of Defense Technology,Changsha 410000,P.R.China)

机构地区：[1]国防科技大学电子科学学院,长沙410073

出　　处：《微电子学》2024年第3期355-361,共7页Microelectronics

基　　金：国家自然科学基金青年基金(62104255)。

摘　　要：基于0.18μm CMOS工艺设计了一款用于ADC前端的采样保持电路,电路采用输入缓冲器-采样开关-输出缓冲器三级结构实现。为提高采样保持电路的保持平稳度,设计了信号馈通和时钟馈通消除结构。为改善频率响应,设计了无源负反馈结构并研究了器件参数对电路性能的影响。仿真结果表明,该馈通消除结构能够提升保持阶段的平稳度,负反馈可将增益提升36 dB。该电路在800 MS/s采样率、122.6 MHz正弦波输入条件下,增益为0 dB,3 dB带宽为1 GHz,信号失真比为48 dB,有效位数为7.7 bit。最终版图面积为202μm×195μm,功耗为37.22 mW,实现了低功耗的设计目标。A sample-and-hold circuit for ADC front-end is designed based on 0.18 μm CMOS process in this paper,and the circuit is realized by using a three-stage structure of input buffer-sample switch-output buffer.In order to improve the steadiness of the sampling and holding circuit,the signal feed-through and clock feed-through elimination structures are designed.To improve the frequency response,a passive negative feedback structure is designed and the effect of device parameters on the circuit performance is investigated.Simulation results show that the feedthrough elimination structure designed in this paper can improve the smoothness of the holding state,and the negative feedback can improve the gain by 36 dB.The circuit has a gain of 0 dB,a 3 dB bandwidth of 1 GHz,a SNR of 48 dB,and an ENOB of 7.7 bit at a sampling rate of 800 MS/s and a 122.6 MHz sine wave input.The layout area is 202 μm × 195 μm and the power consumption is 37.22 mW,which achieves the low-power design goal.

关 键 词：ADC CMOS工艺 低功耗 采样保持电路 馈通消除 

分 类 号：TN432[电子电信—微电子学与固体电子学]