包含过渡区的可自动变模数字锁相环  

Digital Phase-locked Loop with Automatic Mode Change and Transition Zone

作　　者：沈祯 刘成[1] SHEN Zhen;LIU Cheng(School of Microelectronics,Shanghai University,Shanghai 201899,P.R.China)

机构地区：[1]上海大学微电子学院,上海201899

出　　处：《微电子学》2024年第3期375-381,共7页Microelectronics

基　　金：国家重点研发计划项目(2021YFB3200600、2021YFB3200602)。

摘　　要：针对传统的数字锁相环频带窄,速度慢,只能锁定中心频率附近频率的缺点,提出了一种具有快捕区、中捕区、过渡区和慢捕区的可变模可监测频率改变的全数字锁相环。该数字锁相环具有自动变模功能,可在锁定过程中自动改变数字滤波器模的值。针对传统数字锁相环在锁定快结束阶段容易进入慢捕区的缺点,在原有的捕捉区域中增加了过渡区,进一步加快了锁定速度。当输入的参考信号频率较高时,环路锁定速度更快。当参考信号在41.67~500 kHz时,系统最快可以在7.64μs内完成锁定。在锁定过程的后阶段,参考信号与输出信号的相位差个数在1~5个系统时钟中均匀分布,相位差系统时钟个数为5、3、2时的锁定速度快于相位差系统时钟个数为4、1。The traditional ADPLL has the disadvantages of narrow loop band,slow speed,and can only lock the frequency near the center frequency.Therefore,automatic mode change all-digital-phase-locked-loop was proposed,which has fast,middle,transition and slow capture zone.New ADPLL can automatically change the digital filter mode value during the locking process.The addition of transition zone reduces the possibility of traditional ADPLL entering the slow capture zone.When the frequency of reference signal is higher,the lock speed is faster.When the reference signal is 41.67-500 kHz,the system can be locked in 7.64 microseconds at the fastest.In the later stage of the locking process,phase difference of the loop is evenly distributed in 1-5 system clocks.When the number of phase difference system clocks is 5,3,and 2,the lock speed is faster than system clocks is 4,1.

关 键 词：全数字锁相环 VERILOG 自动变模 过渡区 

分 类 号：TN911.8[电子电信—通信与信息系统]