一种采用比例积分和自适应复合控制的全数字锁相环  

All Digital Phase-locked Loop Implemented by Adopting Composite Control of Proportional Integral and Adaptive

作　　者：蒋小军[1] 粟慧龙[1] 刘丽丽[1] 蒋小伟 刘运松 JIANG Xiao-jun;SU Hui-long;LIU Li-li;JIANG Xiao-wei;LIU Yun-song(Hunan Railway Vocational and Technical College,Zhuzhou 412001 China)

机构地区：[1]湖南铁道职业技术学院,湖南株洲412001

出　　处：《自动化技术与应用》2024年第9期97-100,共4页Techniques of Automation and Applications

基　　金：湖南省教育厅科学研究项目(21C1299)。

摘　　要：针对传统全数字锁相环存在着锁定速度慢、锁相精度不高和锁频范围较窄等问题,提出一种采用比例积分与自适应复合控制方式的全数字锁相环,通过“粗调”和“精调”来提高锁定速度以及锁相精度。在QuartusII软件环境下,使用VHDL语言编程,采用自顶向下的模块化设计思路对整个全数字锁相环系统进行电路设计,进行综合编译、仿真和分析,并将程序代码下载到FPGA中进行硬件测试。系统仿真与实验结果表明该锁相环可随输入信号频率的变化实时调节环路的控制参数和自由振荡频率,且具有锁相速度快、功耗低、电路结构简单和易于集成的特点。To solve the problems of a narrow lock frequency range,the loop control parameters and the free oscillation frequency can not be regulated online exist in previous systems,all digital phase-locked loop(ADPLL)implemented by adopting composite control of proportional integral(PI)control and adaptive control is proposed in this paper,improve the phase-locked accuracy and locking speed by“coarse adjustment”and“fine adjustment”.In Quartus II software environment,the entire all digital phase-locked loop circuit structure is devised by VHDL as well as making use of Top-Down and modular design method,and evaluated and analysed based on simulations,and evaluated with Field Programmable Gate Array(FPGA)based on experiments,system simulations and experimental results show the ADPLL can real-time regulate loop control parameters and free oscillation frequency with the input signal frequency changes,it has characteristic of fast locking speed,low power consumption,simple circuit structure and easy system integration.

关 键 词：比例积分控制 自适应控制 全数字锁相环 VHDL FPGA 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]