GaN收发多功能芯片在片集成测试优化  

Optimization of On⁃wafer Integration Testing of GaN Transceiver Multifunctional Chips

作　　者：陈金远[1] 余旭明[1] 王逸铭 丛诗力 葛佳月 戴一凡 CHEN Jinyuan;YU Xuming;WANG Yiming;CONG Shili;GE Jiayue;Dai Yifan(Nanjing Electronic Devices Institute,Nanjing,210016,CHN)

机构地区：[1]南京电子器件研究所,南京210016

出　　处：《固体电子学研究与进展》2024年第4期315-318,共4页Research & Progress of SSE

摘　　要：为了解决传统开关集成测试方案中严苛的时序同步要求,根据GaN收发多功能芯片的在片电参数测试需求,采用环行器优化测试方案,减少芯片测试时序变量,提高了芯片测试程序的鲁棒性,并且利用去嵌入技术对系统的校准进行简化。通过典型器件的测试对方案进行了验证,结果表明,环行器优化测试方案与传统的开关集成测试方案输出结果基本一致,优化测试方案是有效的。In this paper,a circulator was adopted to optimize the testing scheme of GaN transceiv-er multifunctional chips,for solving the strict timing synchronization requirements in traditional switch integration testing schemes.The test timing variables of GaN transceiver multifunctional chips were reduced and the robustness of the chip testing program was improved.The de-embedding technique was used to simplify the calibration of the system.The scheme was validated through testing of typical devices.The results show that the optimized testing scheme with the circulator is consistent with the traditional switch integration testing scheme,thus,the optimized testing scheme is effective.

关 键 词：收发多功能芯片 在片集成测试 测试时序 鲁棒性 去嵌入 

分 类 号：TN407[电子电信—微电子学与固体电子学] TN722.13