浮栅和高压栅极共掺在EEPROM中的应用研究  

Research on the Application of Floating Gate and High⁃voltage Gate Co-doping in EEPROM

作　　者：刘冬华 陈云骢 钱文生 LIU Donghua;CHEN Yuncong;QIAN Wensheng(Shanghai Huahong Grace Semiconductor Manufacturing Corporation,Shanghai,201206,CHN)

机构地区：[1]上海华虹宏力半导体制造有限公司,上海201206

出　　处：《固体电子学研究与进展》2024年第4期363-366,共4页Research & Progress of SSE

摘　　要：为简化电可擦除可编程只读存储器(Electrically-erasable programmable read-only memory, EEPROM)的制造工艺以及减少等离子体对隧道氧化层的损害,重点分析了将浮栅多晶硅和高压器件的栅极共同掺杂对存储器件和高压器件的影响,包括不同掺杂浓度下EEPROM存储单元的擦写速度、读取电流、可靠性以及高压晶体管的电学特性等相关分析,探讨优良器件特性的最优掺杂浓度设计方法,为器件性能优化以及工艺改进提供参考。Based on the perspective of simplifying the process of electrically-erasable programma-ble read-only memory(EEPROM)manufacturing and reducing the damage of plasma to the oxide lay-er of the tunnel,this paper focused on the analysis of the effects of the co-doping of the gate of the floating gate polysilicon and the high-voltage device on the memory device and the high-voltage de-vice,including the analysis of the erasing speed,read current,reliability and electrical characteristics of high-voltage transistor of the EEPROM memory cell under different doping concentrations.This pa-per discussed the optimal doping concentration design method for obtaining better device characteris-tic,which provided an important theoretical basis for device optimization and process improvement.

关 键 词：EEPROM 浮栅 共掺 

分 类 号：TN4[电子电信—微电子学与固体电子学] TM74[电气工程—电力系统及自动化]