基于FPGA的卷积神经网络加速器现状研究  

A survey of convolutional neural network accelerator based on FPGA

作　　者：张坤 高博[1] 冀亚玮 谢宗甫 高飞[1] 李宇东 ZHANG Kun;GAO Bo;JI Yawei;XIE Zongfu;GAO Fei;LI Yudong(School of Information Systems Engineering,Information Engineering University,Zhengzhou Henan 450000,China)

机构地区：[1]战略支援部队信息工程大学信息系统工程学院,河南郑州450000

出　　处：《太赫兹科学与电子信息学报》2024年第10期1142-1153,1167,共13页Journal of Terahertz Science and Electronic Information Technology

摘　　要：近年来,得益于计算机运算能力的提升和互联网所产生的大量数据,深度学习(DL)技术取得了快速发展,其中最显著的卷积神经网络(CNN)在图像识别、目标检测、自然语言处理等领域已经成功实现商用。然而随着网络层数越来越深,对计算能力和内存需求急剧上升,如何对卷积神经网络进行加速并在硬件加速器上部署的问题逐渐成为学术界研究的热点。从现场可编程门阵列(FPGA)开发神经网络的优势出发,介绍了FPGA的多种开发方式,详细论述了部署和加速卷积神经网络的各种优化策略,以及采用不同优化策略的FPGA卷积神经网络加速器的性能表现。最后,展望了FPGA卷积神经网络加速器的未来发展方向。In recent years,thanks to the enhancement of computing power of computers and the vast amount of data generated by the internet,Deep Learning(DL)technology has achieved rapid development.Among them,the most notable Convolutional Neural Networks(CNN)have successfully been commercialized in fields such as image recognition,object detection,and natural language processing.However,as the network layers become deeper,the demand for computing power and memory has risen sharply.How to accelerate convolutional neural networks and deploy them on hardware accelerators has gradually become a hot topic in academic research.Starting from the advantages of developing neural networks with Field-Programmable Gate Arrays(FPGA),various development methods of FPGA are introduced,various optimization strategies for deploying and accelerating convolutional neural networks are discussed in detail,and the performance of FPGA convolutional neural network accelerators using different optimization strategies is presented.Finally,the future development direction of FPGA convolutional neural network accelerators is expected.

关 键 词：卷积神经网络 FPGA加速器 网络压缩 卷积算法 脉动阵列 

分 类 号：TN914.42[电子电信—通信与信息系统]