三维系统级封装(3D-SiP)中的硅通孔技术研究进展  

Review on the through Silicon Via Technology in the 3D-system in Package(3D-SiP)

作　　者：王美玉 张浩波 胡伟波 梅云辉 WANG Meiyu;ZHANG Haobo;HU Weibo;MEI Yunhui(School of Electronic Information and Optical Engineering,Nankai University,Tianjin 300350;Shenzhen Research Institute,Nankai University,Shenzhen 518000;School of Electrical Engineering,Tiangong University,Tianjin 300387)

机构地区：[1]南开大学电子信息与光学工程学院,天津300350 [2]南开大学深圳研究院,深圳518000 [3]天津工业大学电气工程学院,天津300387

出　　处：《机械工程学报》2024年第19期261-276,共16页Journal of Mechanical Engineering

基　　金：国家自然科学基金(52107198);广东省自然科学基金(2023A1515011854);中央高校基本业务费专项资金(63231154)资助项目。

摘　　要：随着系统复杂度的不断提高,传统封装技术已不能满足多芯片、多器件的高性能互联。而三维系统级封装(3D-system in package,3D-SiP)通过多层堆叠和立体互联实现了芯片和器件的高性能集成。其中,硅通孔(Throughsiliconvia,TSV)结构在3D-Si P中发挥着极为关键的作用。系统性的回顾了TSV技术的研究进展,包括TSV的技术背景、生产制造、键合工艺和应用特色,同时对比并总结了不同制造工艺和键合工艺的优缺点,如制造工艺中的刻蚀、激光钻孔、沉积薄膜和金属填充,键合工艺中的焊锡凸点制备、铜柱凸点制备和混合键合,讨论了TSV当前面临的挑战,展望了TSV未来的发展趋势。With the increasing complexity of the system,the traditional packaging technology can no longer meet the high-performance interconnection of multi-chips and multi-devices.3D-system in package(3D-SiP)achieves high-performance integration of chips and devices through multi-layer stacking and stereo interconnection.Among them,the through silicon via(TSV)structure plays a crucial role in 3D-SiP.This study systematically reviewed the TSV technology,including its technical background,manufacturing,bonding process and application features of TSV.In addition,it compared the advantages and disadvantages of different manufacturing processes and bonding processes,such as etching,laser drilling,deposited film and metal filling in manufacturing process,solder bump,copper pillar bump and hybrid bonding in bonding process,summarized the recent research progress and the current challenges,and prospected the development trend of TSV in the future.

关 键 词：三维封装 系统级封装 硅通孔 垂直互联 

分 类 号：TN405[电子电信—微电子学与固体电子学]